基于先进CMOS工艺的多通道Gbps LVDS接收器  

Multi channels Gbps LVDS receiver based on advanced CMOS

作　　者：赵达 沈丹丹 王亚军 杨亮 桂江华 邵健 Zhao Da;Shen Dandan;Wang Yajun;Yang Liang;Gui Jianghua;Shao Jian(CETC Suntai Information Technology Co.,Ltd.,Wuxi 214100,China;No.58 Research Institute,CETC,Wuxi 214035,China)

机构地区：[1]中电科申泰信息科技有限公司,江苏无锡214100 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子技术应用》2024年第5期24-29,共6页Application of Electronic Technique

摘　　要：在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟,并结合ADC的测试模式来确认每一个通道的采样相位,能够自动对每一个通道的延时分别进行调整,以达到对齐各通道采样相位点,保证数据正确采集的目的。最后,基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试,仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位,且最大的采样相位调节范围为±3 bit,信噪比大于65 dB,满足了设计要求和应用需求。When integrating multi-channel high-speed ADC(Analog-to-Digital Converter)with LVDS(Low Voltage Differential Signal)interface in SIP(System In a Package)system,it is faced with the problem of clock-to-data skew,data-to-data skew,accumulated clock jitter and so on caused by different LVDS channel with different delays.Therefore,a multi-channel LVDS receiver was designed in this paper which can adaptively adjust the skew of each LVDS channel.The receiver uses data clock recovery technology to generate eight multi-phase sampling clocks,combining with ADC test mode to confirm the sampling phase of each channel,the delay of each channel can be automatically adjusted,aiming to align the sampling phase of channels and ensure the data correct.Finally,the receiver was designed,simulated,and realized based on advanced CMOS technology.The results of simulation and chip test show that the receiver can automatically adjust the delay of each channel to align the sampling phase,the maximum range of sampling phase adjustment is±3 bit,and the signal-to-noise ratio is greater than 65 dB,which meets the design requirements and application requirements.

关 键 词：模数转换器 多通道LVDS 锁相环 时钟数据恢复 

分 类 号：TN432[电子电信—微电子学与固体电子学]