金凸点芯片倒装键合的失效分析方法  

Failure Analysis Method of Flip-chip Bonding on Gold Bumped Chips

作　　者：柳溪溪 冀乃一 邢增程 LIU Xixi;JI Naiyi;XING Zengcheng(The 13th Research Institute of CETC,Shijiazhuang 050000,China)

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050000

出　　处：《电子工艺技术》2024年第3期21-24,共4页Electronics Process Technology

摘　　要：给出了倒装芯片金凸点倒装键合失效的主要界面形式。以制备的直径为60±5μm金凸点的Si芯片-GaAs芯片形式的倒装芯片作为研究样品,试验了业界常用的无损检测技术以及破坏性检测技术对倒装芯片堆叠界面的观测效果。其中工业CT、制样研磨的方式可较好地观测堆叠失效界面的细节信息。最后给出了倒装芯片失效分析的定位思路,并采用失效芯片进行了验证,对倒装芯片的失效分析有一定的指导意义。The main forms of gold bump flip-flop bonding failure in flip chip are given.Flip-chips in the form of Si chip-GaAs chip with 60±5µm diameter gold bumps are prepared as research samples,then the observation of flip-chip stacked interfaces by NDT and destructive testing techniques commonly used in the industry is experimented.Industrial CT,sample preparation and grinding can be used to better observe the details of the stack failure interface.Finally,the localization idea offlip chip failure analysis is given and verified using a failed chip,which is a guide to the failure analysis of flip chip.

关 键 词：金凸点 倒装键合 无损检测 失效分析 

分 类 号：TN406[电子电信—微电子学与固体电子学]