一种应用于DDR的低抖动锁相环设计  

Design of Low-Jitter Phase-Locked Loop Applied to DDR

作　　者：华佳强 李野[1] HUA Jiaqiang;LI Ye(School of Physics,Changchun University of Science and Technology,Changchun 130022,China)

机构地区：[1]长春理工大学物理学院,长春130022

出　　处：《电子与封装》2024年第5期65-71,共7页Electronics & Packaging

摘　　要：针对双倍速率同步动态随机存储器中锁相环抖动性能较差的问题,基于55nmCMOS工艺设计了一种低抖动锁相环。采用负反馈型比例-积分结构控制的电荷泵来获得良好的抖动性能并实现快速锁定,环型振荡器采用伪差分结构的预充电方式来提升时钟翻转速度。后仿真结果显示,在2.5V电源供电条件下,锁相环能够在2μs内锁定在3.2GHz频率处,其相位噪声约为-96.2dBc/Hz@1MHz。芯片测试结果显示,输出时钟周期抖动为-27.7~23.2ps。Aiming at the problems of poor jitter performance of phase-locked loops in double-data rate synchronous dynamic random access memories,a low-jitter phase-locked loop is designed based on the 55 nm CMOS process.A charge pump controlled by negative feedback proportional integration structure is used to obtain good jitter performance and achieve fast lock-up,and the ring oscillator is pre-charged with a pseudo-differential structure to improve the clock flipping speed.The post-simulation results show that under the condition of 2.5 V power supply,the phase-locked loop can be locked at 3.2 GHz in 2μs,and its phase noise is about-96.2 dBc/Hz@1 MHz.The chip test results show that the output clock cycle jitter is-27.7-23.2 ps.

关 键 词：锁相环 负反馈电荷泵 预充电环形振荡器 

分 类 号：TN402[电子电信—微电子学与固体电子学]