基于55 nm CMOS工艺的小数分频电荷泵锁相环设计  

Design of fractional frequency division charge pump PLL based on 55 nm CMOS process

作　　者：李金凤 郭瑞华 凌辛旺 于德明 LI Jinfeng;GUO Ruihua;LING Xinwang;YU Deming(School of Information Engineering,Shenyang University of Chemical Technology,Shenyang 110142,China)

机构地区：[1]沈阳化工大学信息工程学院,辽宁沈阳110142

出　　处：《电子设计工程》2024年第12期71-75,共5页Electronic Design Engineering

摘　　要：为解决无线射频收发机中锁相环存在的功耗高、精度低、不能小数分频等问题,提出了一种基于55 nmCMOS工艺的小数分频电荷泵锁相环,降低噪声对电路性能的影响,为无线收发机提供稳定的震荡信号。采用三阶噪声整形结构的数字Σ-Δ调制器,设计了24位高精度可编程小数分频器。同时设计了一种线性移位寄存器,产生随机数列降低小数杂散。采用单位增益缓冲器有效地降低了电荷泵的电流失配。SPECTRE仿真结果表明,电荷泵的充放电流失配为0.87%,锁相环的输出频率范围为2.1~2.9 GHz,相位噪声为-108 dBc/Hz@1 MHz,分频比为5~128,锁定时间小于3.5μs,功耗为8.56 mW。In order to solve the problems of high power consumption,low accuracy,and no fractional division in the phase⁃locked loop in the radio frequency transceiver,a fractional charge⁃pump phase⁃locked loop based on the 55 nm CMOS process is proposed to reduce the influence of noise on circuit performance and provide a stable oscillation signal for the wireless transceiver.A digitalΣ-Δmodulator with a third⁃order noise shaping structure is used to design a 24 bit high⁃precision programmable fractional divider.At the same time,a linear shift register is designed to generate a random sequence of numbers to reduce decimal spurs.The use of a unity⁃gain buffer effectively reduces the current mismatch of the charge pump.The SPECTRE simulation results show that the charge pump has a charge⁃discharge loss configuration of 0.87%,the output frequency range of the phase⁃locked loop is 2.1~2.9 GHz,the phase noise is-108 dBc/Hz@1 MHz,the divide⁃by⁃frequency ratio is 5~128,the lock⁃up time is less than 3.5μs,and the power consumption is 8.56 mW.

关 键 词：电荷泵 锁相环 小数分频 Σ-Δ调制器 

分 类 号：TN75[电子电信—电路与系统]