面向多通道冗余系统的FPGA硬件脉冲同步方法研究  

Research on FPGA Hardware Pulse Synchronization Method for Multi-channel Redundant Systems

作　　者：季浩 刘凯[1] 孙献毓 王忠尉 杨国均 姚佳烽 JI Hao;LIU Kai;SUN Xianyu;WANG Zhongwei;YANG Guojun;YAO Jiafeng(College of Mechanical and Electrical Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China;AECC Aero-Engine Control System Institute,Wuxi 214063,China)

机构地区：[1]南京航空航天大学机电学院,江苏南京210016 [2]中国航发控制系统研究所,江苏无锡214063

出　　处：《机械制造与自动化》2024年第3期10-14,共5页Machine Building & Automation

摘　　要：提出一种基于现场可编程门阵列(FPGA)的硬件脉冲同步方法以保证冗余系统数据交互、任务调度的可靠性。以三通道冗余系统为例,每个通道都接收3个通道的脉冲信号输入,对3个通道的脉冲信号进行排序,确定主控通道的脉冲同步信号;捕获主控脉冲的信号边沿,计算与另外两个通道的同步偏差;设置不同粒度的调整区间,偏差大进行多周期调整,偏差小则进行单周期调整;建立基于FPGA的硬件脉冲同步仿真平台并进行测试分析。仿真结果表明:脉冲同步精度可达到20 ns,同步建立时间不超过470 ms,满足了多通道冗余系统的同步需求。A hardware pulse synchronization method based on field programmable gate array(FPGA)is proposed to ensure the reliability of data interaction and task scheduling of the redundant system.Taking the three-channel redundant system as an example,each channel receives pulse signal inputs from three channels,the pulse signals of the three channels are sorted to determine the pulse synchronization signal of the master channel.The signal edges of the master pulse are captured to compute the synchronization deviation from the other two channels.The adjustment intervals with different granularities are set with large deviations for multi-cycle adjustment and small deviations for single-cycle adjustment.The FPGA-based hardware pulse synchronization simulation platform is established and simulated.The simulation results show that the pulse synchronization accuracy can reach 20 ns,and the synchronization establishment time is no more than 470 ms,which meets the synchronization requirements of multi-channel redundant system.

关 键 词：冗余 多通道 硬件同步 FPGA 

分 类 号：V233.7[航空宇航科学与技术—航空宇航推进理论与工程]