HARP-SiCoNi工艺在量产环境下提升高台阶比浅沟道隔离填充能力的研究  

Study on the Improvement of the HARP-SiCoNi Process in the Mass Production Environment to Improve the Filling Capacity of High Step Ratio Compared to Shallow Trench Isolation

作　　者：倪立华 丁亚钦 李宗旭 NI Lihua;DING Yaqin;LI Zongxu(Shanghai Huahong Grace Semiconductor Manufacturing Corporation,Shanghai 201203,China)

机构地区：[1]上海华虹宏力半导体制造有限公司,上海201203

出　　处：《集成电路应用》2024年第4期52-54,共3页Application of IC

摘　　要：阐述基于量产环境中“高台阶比”的“非标准V型”STI结构,使用传统的HARP和SiCoNi组合工艺研究该结构Void Free的填充方案,并测试HARP预沉积厚度和SiCoNi刻蚀量的工艺窗口,实现量产环境下“高台阶比”的“非标准V型”沟槽Void Free填充。This paper describes the“non-standard V-type”STI structure with“high step ratio”in mass production environment,the void free filling scheme of the structure using the traditional combination of HARP and SiCoNi process,and the process window of HARP pre-deposition thickness and SiCoNi etching amount in testing,so as to release the void free filling of“non-standard V-shaped”trench with“high step ratio”in mass production environment.

关 键 词：集成电路制造 STI填充 HARP SiCoNi VOID 

分 类 号：TN405[电子电信—微电子学与固体电子学]