基于FPGA的SM4算法高效实现方案  

Efficient implementation scheme of SM4 algorithm based on FPGA

作　　者：张宏科 袁浩楠[3,4] 丁文秀 闫峥 李斌[2] 梁栋 ZHANG Hongke;YUAN Haonan;DING Wenxiu;YAN Zheng;LI Bin;LIANG Dong(School of Cyber Engineering,Xidian University,Xi’an 710126,China;The 54th Research Institute of China Electronics Technology Group Corporation,Shijiazhuang 050299,China;State Key Laboratory of Integrated Services Networks,Xidian University,Xi’an 710071,China;Hangzhou Institute of Technology,Xidian University,Hangzhou 311200,China)

机构地区：[1]西安电子科技大学网络与信息安全学院,陕西西安710126 [2]中国电子科技集团公司第五十四研究所,河北石家庄050299 [3]西安电子科技大学空天地一体化综合业务网全国重点实验室,陕西西安710071 [4]西安电子科技大学杭州研究院,浙江杭州311200

出　　处：《通信学报》2024年第5期140-150,共11页Journal on Communications

基　　金：国家自然科学基金资助项目(No.U23A20300,No.62072351);陕西省自然科学基础研究计划重点基金资助项目(No.2023-JC-ZD-35);陕西省自然科学基础研究计划基金资助项目(No.2023-JC-YB-500)。

摘　　要：针对SM4算法的FPGA实现方案存在数据处理速度不够高和逻辑资源占用过高的问题,提出了基于现场可编程门阵列(FPGA)的高性能、低资源消耗的SM4算法实现方案。所提方案采用循环密钥扩展与32级流水线加解密相结合的架构,循环密钥扩展的方式降低了逻辑资源消耗,32级流水线加解密的方式提高了数据吞吐率。同时,所提方案采用代数式S盒并通过合并线性运算以及在不可约多项式的合并矩阵中筛选最优矩阵运算的方式进一步减少S盒变换的运算量,从而达到降低逻辑资源占用与提高工程数据吞吐率的目的。测试结果显示,该方案比现有最佳方案在数据吞吐率上提升了43%,且资源占用率降低了10%。To address the inefficient data processing performance and excessive resource utilization issues that field-programmable gate array(FPGA)-based SM4 implementations faced,an implementation scheme that adopted both itera‐tion and pipeline in order to reduce resource consumption and improve throughput was proposed.A combination of cy‐clic key extension and 32 bit pipeline encryption and decryption architecture was adopted by the proposed scheme.The cyclic key extension reduced logical resource consumption,while the 32 bit pipeline encryption and decryption improved data throughput.Additionally,an algebraic S-box that combined linear operations to select an optimal matrix from those generated by different irreducible polynomials was employed.Resource usage and computation overhead was further minimized,thus achieving an increased engineering frequency.Experimental results demonstrate a 43%throughput im‐provement and a 10%reduction in resource usage compared to the current best scheme.

关 键 词：SM4算法 FPGA实现 流水线架构 代数式S盒 

分 类 号：TN92[电子电信—通信与信息系统]