通用信道编译码算法物理性能快速仿真系统  

Fast simulation system for physical performance of universal channel codecs

作　　者：秦明伟[1] 高永翔 李陈 侯宝临[1] 王焕[1] QIN Mingwei;GAO Yongxiang;LI Chen;HOU Baolin;WANG Huan(School of Information Engineering,Southwest University of Science and Technology,Mianyang 621010,China)

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010

出　　处：《中国测试》2024年第6期98-105,共8页China Measurement & Test

基　　金：国家自然科学基金(62261051);四川省科技厅应用基础面上项目(2019YJ0309)。

摘　　要：为实现信道编译码硬件算法物理性能的快速、准确验证,提出一种软硬件协同的通用化信道编译码算法物理性能快速仿真与性能评估系统。PC上位机软件主要实现模拟信源/噪声数据生成、仿真数据后分析、数据/控制指令传输以及与FPGA下位机交互等功能;FPGA下位机通过设计数据调度与系统控制、信道编译码算法架构、加噪信道以及数据统计等单元,构建通用编译码算法验证系统硬件系统架构,支持不同信道编译码算法物理性能的高效、准确验证。以系统当前支持的BCH码、LDPC码、删余卷积码、RS码及其串行级联码的性能仿真为例开展性能测试,性能恶化最大值低于0.4 dB,在10-7误码率统计量级下,仿真时间低于12 s,验证仿真评估系统的准确性、可靠性与有效性。系统采用的通用级联架构还可支持其他信道编译码算法的快速移植与部署,可为信道编译码算法物理性能快速验证提供一种有效的解决方案。In order to realize fast and accurate verification of physical performance of hardware implementation algorithm of channel coding and decoding,the paper proposed and designed a universal system with software�hardware collaboration for fast simulation and evaluation of physical performance of channel coding and decoding algorithm.The PC mainly realized the generation of analog source data and noise data,data analyzing after simulation,command transmission of data or control as well as interacting with FPGA.The hardware system architecture of the universal algorithm verification system was constructed in this paper through designing the mechanism of data scheduling and system control,architecture of channel coding and decoding algorithm as well as the unit of noise adding channel and data statistics in FPGA,leading to supporting efficient and accurate verification of physical performance of different channel coding and decoding algorithms.The performance test is carried out by taking the performance simulation of BCH code,LDPC code,punctured convolutional code,RS code and its serial concatenated code currently supported by the system as an example,the maximum performance degradation is lower than 0.4 dB,under the statistical magnitude of 10-7 bit error rate,the simulation time is less than 12 seconds,which verified the accuracy,reliability and effectiveness of the simulation and evaluation system.The universal cascading architecture adopted by the system can also support the rapid migration and deployment of other channel coding and decoding algorithms,providing an effective solution for the rapid verification of the physical performance of channel coding and decoding algorithms.

关 键 词：信道编译码 物理性能 仿真系统 软硬件协同 加噪信道 

分 类 号：TB9[一般工业技术—计量学] TN98[机械工程—测试计量技术及仪器]