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作 者:陈煌伟 陈智峰 陈继明 黄新栋 陈铖颖 CHEN Huangwei;CHEN Zhifeng;CHEN Jiming;HUANG Xindong;CHEN Chengying(School of Opto-Electronic and Communication Engineering,Xiamen University of Technology,Xiamen 361024,China)
机构地区:[1]厦门理工学院光电与通信工程学院,福建厦门361024
出 处:《厦门理工学院学报》2024年第3期58-65,共8页Journal of Xiamen University of Technology
基 金:福建省自然科学基金引导性项目“低功耗智能语音SoC芯片研究与实现”(2023H0052);厦门市重大科技项目“助听器DSP处理器芯片及设备的研发与产业化”(3502Z20221022);福建省自然科学基金项目“高带宽serdes芯片研究与实现”(2022J011273)。
摘 要:针对传统电荷泵较低负载能力和较高纹波的问题,基于SMIC 0.18μm CMOS工艺,设计一款四相非交叠时钟的低纹波电荷泵电路。电荷泵主体电路由2个四相时钟控制的全PMOS电荷泵交叉耦合构成;通过优化时序信号输入,降低传输管的导通电阻,减小传输损耗和尖峰脉冲,提高输出效率,同时压缩输出纹波;采用动态衬底偏置结构以消除体效应影响,提高各级升压电路的稳定性,进一步减小输出纹波。仿真结果表明,在电源电压为1.8 V、负载电流为5 mA时,电荷泵输出电压值约为5 V,上升时间约为3.67μs,电压纹波仅为5.4 mV,表明本设计可以满足高可靠堆叠闪存芯片的电压需求。In response to the issues of low load capacity and high ripple in traditional charge pumps,this paper proposes the design of a low-ripple charge pump circuit with a four-phase non-overlapping clock based on the SMIC 0.18μm CMOS process.The main circuit of the charge pump consists of two fully PMOS charge pumps cross-coupled with a four-phase clock control.By optimizing the timing signal input to reduce the on-resistance of the transfer transistors,this design lowers the conduction resistance,and decreases transmission losses and peak pulses,thereby compressing output ripple while enhancing output efficiency.The utilization of a dynamic substrate biasing structure is employed to eliminate the impact of body effects,thereby improving the stability of each boost circuit and further reducing the output ripple.Subsequent simulation results indicate that,with a power supply voltage of 1.8 V and a load current of 5 mA,the charge pump achieves an output voltage of approximately 5 V,a rise time of about 3.67μs,and a voltage ripple of only 5.4 mV.This indicates that this design meets the voltage requirements of highly reliable stacked flash memory chips.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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