LTE Cat.1物联网芯片物理层设计与开发  

Design and Development of Physical Layer for LTE Cat.1 IoT Chips

作　　者：吴晓荣 Wu Xiaorong(Xinmai Micro Semiconductor(Shanghai)Co.,Ltd.,Shanghai,China)

机构地区：[1]芯迈微半导体(上海)有限公司,上海

出　　处：《科学技术创新》2024年第15期75-78,共4页Scientific and Technological Innovation

摘　　要：本文结合芯迈微半导体的Cat.1物联网芯片开发项目展开研究,首先简要介绍项目开发情况;然后重点阐述了物理层功能的软硬件协同开发流程、软硬件划分、ASIC设计的硬件资源与时序优化,以及功耗相关的软硬件设计;最后规划清晰的芯片验证路径,有效暴露ASIC模块的设计问题。This article conducts research on the Cat.1 IoT chip development project of Xinmai Micro Semiconductor.Firstly,it briefly introduces the project development situation;Then,the focus was on elaborating the software and hardware collaborative development process of physical layer functions,software and hardware division,hardware resources and timing optimization of ASIC design,as well as power consumption related software and hardware design;Finally,plan a clear chip verification path to effectively expose the design issues of the ASIC module.

关 键 词：Cat.1 LTE通信芯片 通信物理层 芯片验证 

分 类 号：TN929[电子电信—通信与信息系统]