基于晶圆级技术的PBGA电路设计与验证  

Design of PBGA circuit based on wafer level packaging technology

作　　者：文永森 罗曦 杜映洪 刘勇 刘绍辉 Wen Yongsen;Luo Xi;Du Yinghong;Liu Yong;Liu Shaohui(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子技术应用》2024年第7期55-58,共4页Application of Electronic Technique

摘　　要：晶圆级封装技术可实现多芯片互连,但在封装尺寸、叠层数和封装良率等方面的问题限制了其在电路小型化进程中的发展。以一款扇出型晶圆级封装电路为例,基于先进封装技术,采用软件设计和仿真优化方式,结合封装经验和实际应用场景,通过重布线和芯片倒装的方式互连,完成了有机基板封装设计与制造,实现了该电路低成本和批量化生产的目标。本产品的设计思路和制造流程可为其他硬件电路微型化开发提供参考。Wafer level packaging technology can achieve multi-chip interconnection.However,issues such as packaging size,number of layers,and packaging yield have limited its development in the process of circuit miniaturization.This article takes a fan out wafer level packaging circuit as an example.Based on advanced packaging technology,using software design and simulation optimization methods,combined with packaging experience and practical application scenarios,the organic substrate packaging design and manufacturing were completed through rewiring and chip flip chip interconnection,achieving the goal of low-cost and mass production of the circuit.The design concept and manufacturing process of this product can provide reference for the miniaturization development of other hardware circuits.

关 键 词：晶圆级封装 电路小型化 芯片倒装 有机基板封装 

分 类 号：TN402[电子电信—微电子学与固体电子学]