80 Gbit/s PAM4光接收机低噪声模拟前端电路设计  

Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver

作　　者：张春茗 王浩 宋茹雪 ZHANG Chunming;WANG Hao;SONG Ruxue(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710199,P.R.China)

机构地区：[1]西安邮电大学电子工程学院,西安710199

出　　处：《微电子学》2024年第2期201-206,共6页Microelectronics

基　　金：100 G光传输系统研究与应用示范国际合作项目(2019YFB1803600)。

摘　　要：采用UMC 28 nm CMOS工艺,设计了一款应用于光接收机、工作在80 Gbit/s PAM4的低噪声模拟前端电路(AFE)。对噪声和带宽进行折中设计,采用了跨阻放大器(TIA)级联连续时间线性均衡器(CTLE)技术和输入电感峰化技术。为了更好地控制低频增益,进一步拓展带宽,采用了跨导跨阻(g_(m)-TIA)结构的VGA。在输入电容100 fF和供电电压1.2 V下,实现的跨阻增益为48.5 dBΩ,带宽为36.1 GHz,平均等效输入噪声电流为22.6pA/√Hz,功耗为14.5 mW。A low-noise analog front-end circuit(AFE)was designed using UMC 28 nm CMOS technology for optical receivers operating at 80 Gbit/s PAM4.To address the tradeoff between the noise and bandwidth,we adopted a trans-impedance amplifier(TIA)cascaded continuous time linear equalizer(CTLE)and input inductor peaking.A VGA with trans-conductance and a trans-impedance(g_(m)-TIA)structure was adopted to effectively control the low-frequency gain and further expand the bandwidth.The circuit achieves a trans-impedance gain of 48.5 dBΩ,a bandwidth of 36.1 GHz,an average equivalent input current noise of 22.6 pA/√Hz,and a power consumption of 14.5 mW,under the conditions of an input capacitance of 100 fF and a supply voltage of 1.2 V.

关 键 词：PAM4编码 跨阻放大器 级联连续时间线性均衡器 可变增益放大器 

分 类 号：TN432[电子电信—微电子学与固体电子学]