一种同步流水线SRAM读写控制模型  

Read-Write Control Model for Synchronous-Pipelined SRAM

作　　者：李铁虎 黄丹[3] 罗华军 祁宗 LI Tiehu;HUANG Dan;LUO Huajun;QI Zong(Chongqing High-Tech Zone Pegasus Innovation Institute,Chongqing 400000,P.R.China;School of Artificial Intelligence,Chongqing University of Technology,Chongqing 401135,P.R.China;Chinese Academy of Ordnance Sciences,Beijing 100089,P.R.China)

机构地区：[1]重庆高新区飞马创新研究院,重庆400000 [2]重庆理工大学两江人工智能学院,重庆401135 [3]中国兵器科学研究院,北京100089

出　　处：《微电子学》2024年第2期228-234,共7页Microelectronics

基　　金：国家自然科学基金资助项目(62004020);重庆市教委科学技术研究项目(KJQN202101137)。

摘　　要：设计了一种同步流水线静态随机存储器读写控制系统的行为级模型。分析了存储器芯片的控制信号和工作时序要求,利用Verilog硬件描述语言对存储器芯片的读写系统进行了行为级建模。系统包括主机、总控制器和存储器三部分,其中总控制器又包括信号源发生器和数据收发控制器两个子模块。利用Modelsim软件对系统行为级模型进行了仿真验证,结果表明系统控制模型在非猝发(常规)、线性猝发、交织猝发三种工作模式下均可对存储器进行正确读写操作。该模型将主机端源控制信号数量减至最少,极大简化了读写控制流程;采用系统时钟双沿对数据采样传输,提升了系统的稳定性。A behavioral model of a read-write control system for synchronous-pipelined static random access memory(SRAM)was designed.The control signals and working timing requirements of the SRAM chip were analyzed,and a behavioral model of a read-write system for the SRAM chip was built using Verilog hardware description language.The system consists of three components,the host,main controller,and memory chip,with the main controller further comprising two submodules,the signal source generator and data transceiver controller.The system behavioral model was simulated and verified using ModelSim software.The simulation results show that the system control model can read and write the SRAM chip correctly in non-burst(regular),linear burst,and interleaved burst operation modes.The number of source control signals from the host decreases to the minimum;thus,the read and write control procedure is considerably simplified.The data are sampled and transmitted with the double edges of the system clock,thus improving the stability of the system.

关 键 词：SRAM 读写控制系统 VERILOG硬件描述语言 行为级模型 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构] TN402[自动化与计算机技术—计算机科学与技术]