一种用于体域网接收机的多路缓冲器设计  

Design of a Multichannel Buffer for Body Area Network Receiver

作　　者：韩泽浩 蒋大海 李政 单强[1] 魏子辉[1] 肖津津[1] 黄水龙[1] HAN Zehao;JIANG Dahai;LI Zheng;SHAN Qiang;WEI Zihui;XIAO Jinjin;HUANG Shuilong(Beijing Key Laboratory of New Generation Radio Frequency Chip Technology for Communication,Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,P.R.China;University of Chinese Academy of Sciences,Beijing 100029,P.R.China)

机构地区：[1]中国科学院微电子研究所新一代通信射频芯片技术北京市重点实验室,北京100029 [2]中国科学院大学,北京100029

出　　处：《微电子学》2024年第3期395-403,共9页Microelectronics

基　　金：国家重点研发计划资助项目(2019YFB2204500)。

摘　　要：设计了一种基于0.35μm CMOS工艺的多通道缓冲器电路,该电路可用于多路接收机中的输出级,以改善输出级的驱动能力。为了应对多路接收机输出端多路缓冲器的设计需求,电路以多个缓冲器为核心,结合多级寄存器、开关阵列,使芯片具备可编程功能。该电路利用多级寄存器每一级的控制信号,实现了在传输过程中通道、缓冲器的切换,控制信号可以采用串行、并行两种传输方式写入。电路的测试结果表明,芯片具备串行、并行两种指令写入方式的功能,缓冲器的-3 dB带宽达到36 MHz,压摆率达到330 V/μs。A multi-channel buffer circuit based on 0.35 μm CMOS technology was designed.It can be utilized as the output stage in a multi-receiver system to enhance the driving capability of the output.The circuit is centered around multiple buffers and integrated multi-level registers and a switch array to satisfy the design requirements of multiple-channel buffers at the output of a multi-receiver system.This configuration provides the chip with programmable functionality.By utilizing control signals at each stage of the multi-level registers,the circuit can independently switch channels and buffers during the transmission process.These control signals can be written using either serial or parallel transmission modes.Test results for the circuit demonstrated its ability to support both serial and parallel instruction-writing modes.The-3 dB bandwidth of the buffer can reach 36 MHz,and the slew rate can reach 330 V/μs.

关 键 词：开关阵列 CMOS工艺 缓冲器 体域网 

分 类 号：TN432[电子电信—微电子学与固体电子学]