一种3.32 mW 0.1~2.0 GHz宽带接收机芯片设计  

Chip Design of a 3.32 mW Broadband Receiver Covering 0.12.0 GHz

作　　者：胡棒 张宸睿 郑乐城 杨定坤 HU Bang;ZHANG Chenrui;ZHENG Yuecheng;YANG Dingkun(College of Physics,East China University of Science and Technology,Shanghai 200237,P.R.China;Corpro,Chengdu 610093,P.R.China)

机构地区：[1]华东理工大学物理学院,上海200237 [2]成都振芯科技股份有限公司,成都610093

出　　处：《微电子学》2024年第3期444-449,共6页Microelectronics

基　　金：国家级大学生创新训练项目(202210251085)。

摘　　要：基于TSMC 65 nm CMOS工艺设计了一种工作频率覆盖0.1~2.0 GHz的宽带低功耗零中频射频接收机芯片。提出的接收机主要包含了无电感宽带低噪声放大器、无源混频器以及中频滤波器模块。其中,滤波器模块通过采用反相器替代了传统的跨阻放大器或者有源低通滤波器,在降低功耗的同时避免使用大量电容、电阻,达到了低功耗、小型化的目的。提出的接收机电路通过Cadence Explore工具后仿真验证,在1.2 V的电源电压下,通道增益约为57 dB,通道噪声系数约低于5.4 dB,三阶输入交调点大于-16.2 dBm,输入1 dB压缩点约-9.7 dBm@2 GHz,中频带宽为190 MHz,带外抑制在30倍频处为83 dBc,电路总静态功耗仅3.32 mW。Based on the TSMC 65 nm CMOS process,this study proposes a circuit of a wideband and low-power ZIF receiver chip.Its working frequency can cover 0.1-2 GHz.The receiver primarily comprises inductorless wideband low-noise amplifiers,passive mixers,and an intermediate frequency filter.In this study,the conventional transimpedance amplifier or active low-pass filter was replaced by an analog inverter to reduce power consumption and avoid using many capacitors and resistors.This also reduced the layout area.The receiver circuit was simulated using Cadence Explore.At a supply voltage of 1.2 V,the channel gain was approximately 57 dB,channel noise figure was about 5.4 dB,third-order input intermodulation point was more than-16.2 dBm,and P1dB was-9.7 dBm @2 GHz.The IF bandwidth was 190 MHz,and the quiescent power consumption of circuit was only 3.32 mW.

关 键 词：低噪声放大器 无源混频器 反相器 滤波器 低功耗 

分 类 号：TN850[电子电信—信息与通信工程] TN722