面向存算架构的神经网络数字系统设计  

Design of neural network digital system for compute-in-memory

作　　者：卢北辰 杨兵[1] LU Beichen;YANG Bing(School of Information,North China University of Technology,Beijing 100144,China)

机构地区：[1]北方工业大学信息学院,北京100144

出　　处：《微电子学与计算机》2024年第9期98-109,共12页Microelectronics & Computer

基　　金：北京市教委研发计划(KZ202210009014)。

摘　　要：随着深度学习与神经网络的不断发展,庞大的计算量使得传统的冯·诺依曼架构设备面临“存储墙”等问题,因此“存内计算(Compute-In-Memory,CIM)”成为满足神经网络高时效需求和高运算量要求的主流设计方向。针对高密度数据的高性能计算提供高速且节能的解决方案,设计了一款神经网络加速器。首先,完成了对ResNet14神经网络的量化,依据其结构设计了一种面向存内计算的数字系统。而后,为了增强该系统的多网络适配性,提出了一种兼容性架构构想,使该数字系统可适配ResNet18或其他卷积神经网络的部分卷积层。最后,将该系统加载到FPGA上进行验证。在10 MHz的时钟频率下,以Cifar-10和MNIST数据集进行目标分类任务,分别得到60 FPS下84.17%和98.79%的准确率,具有更小的数据位宽和相近的准确率。With the continuous development of deep learning and neural networks,the immense computational demand presented challenges for traditional von Neumann architecture devices.Consequently,Compute-In-Memory(CIM)become the prevailing design direction to meet the high timeliness requirements and compute-intensive demands of neural networks.A dedicated neural network accelerator is designed to provide high-speed solutions for high-density data.The ResNet14 neural network is quantified at first,and a digital system oriented towards Compute-In-Memory is designed based on net's structure.To enhance the system’s adaptability to multiple networks,a compatibility concept is proposed,enable the digital system to accommodate partial convolutional layers of ResNet18 or other convolutional neural networks(CNN).Finally,the system is deployed on an FPGA for verification.Under a clock frequency of 10 MHz,target classification tasks are performed on the Cifar-10 and MNIST datasets,resulting in accuracy rates of 84.17%and 98.79%respectively at 60 FPS,that means this design has smaller data width and similar accuracy.

关 键 词：存内计算 数字集成电路设计 目标分类 卷积神经网络 ResNet14 

分 类 号：TN403[电子电信—微电子学与固体电子学]