An effective fault localization approach for Verilog based on enhanced contexts  

作　　者：Zhuo ZHANG Ya LI Lei XIA Jianxin XUE Jiang WU Xiaoguang MAO 

机构地区：[1]School of Computer Science and Engineering,Xi'an University of Technology,Xi'an 710048,China [2]Ningbo Artificial Intelligence Institute,Shanghai Jiao Tong University,Ningbo 315000,China [3]No.83 Army Joint and Truma Disease Treatment Centre of PLA,Xinxiang 453000,China [4]Department of Software Engineering,Shanghai Second Polytechnic University,Shanghai 201209,China [5]College of Computer,National University of Defense Technology,Changsha 410073,China

出　　处：《Frontiers of Computer Science》2024年第5期223-225,共3页计算机科学前沿（英文版）

基　　金：This work was partially supported by the Guangdong Province Ordinary University Characteristic Innovation Project(2023KTSCX193).

摘　　要：New computer architecture innovationswith diverse functionalities and comprehensive features continue to emerge incessantly,resulting in a rising trend of incorporating a larger number of circuit devices into these products[1].In the case of a sophisticated and expansive integrated circuit chip,the presence of defective or malfunctioning components can significantly impact the overall performance of the circuit.This situation may even result in costly repercussions.

关 键 词：VERILOG COMPUTER circuit. 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程]