3D封装中硅通孔的电-热-结构耦合分析  

Electrical-thermal-structural Coupling Analysis of Through Silicon Vias in 3D Packaging

作　　者：张远乐 龚瑜璠 陈召川 赵起 孟欣 李强[1] 陈雪梅 ZHANG Yuanle;GONG Yufan;CHEN Zhaochuan;ZHAO Qi;MENG Xin;LI Qiang;CHEN Xuemei(School of Energy and Power Engineering,Nanjing University of Science and Technology,Nanjing 210094,China)

机构地区：[1]南京理工大学能源与动力工程学院,电子设备热控制工信部重点实验室,南京210094

出　　处：《工程热物理学报》2024年第11期3508-3516,共9页Journal of Engineering Thermophysics

基　　金：国家自然科学基金资助项目(No.U2241252,No.52276071)。

摘　　要：本文利用有限元分析软件对3D集成芯片中不同形状的硅通孔(TSV)结构进行电–热–结构耦合分析。研究结果表明:圆环形TSV的应力水平远小于圆柱形和圆锥形TSV。在相同激励电压下,减小TSV直径、增大TSV高度、减小SiO_(2)厚度均可提高TSV的可靠性。对圆环形TSV进行正交实验发现,TSV的直径和中间介质对最高温度、最大应力影响程度较大。在单层TSV阵列中,当中心间距较小时,圆环形TSV出现应力叠加现象,应力叠加水平受中心间距与排列方式的影响。In this paper,the electric-thermal-structural coupling analysis of different structures of through silicon via(TSV)with different shapes in 3D integrated chips is performed with finite element analysis(FEA)software.The results reveal that the stress level of circular TSV is much smaller than cylindrical and conical TSV.At the same excitation voltage,the reliability of TSV can be improved by decreasing the TSV diameter,increasing the TSV height,and decreasing the thickness of SiO_(2).The orthogonal experiments on circular TSV indicate that a greater effect of the diameter and intermediate medium of the TSV on the maximum temperature and maximum stress is achieved.In single-layer TSV arrays,the phenomenon of stress superposition is observed in circular TSV when the centre spacing was small,and the level of stress superposition is affected by the center spacing and array arrangement.

关 键 词：硅通孔 电–热–结构 耦合分析 3D封装 

分 类 号：TK02[动力工程及工程热物理]