基于22nm工艺的GNSS芯片片上偏差的时序分析  

Timing analysis of on-chip variation for GNSS chips based on the 22 nm process

作　　者：符强[1,2,3] 黄三峰 纪元法 肖有军[4] 屈康杰 梁家瑞 FU Qiang;HUANG Sanfeng;JI Yuanfa;XIAO Youjun;QU Kangjie;LIANG Jiarui(Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin University of Electronic Technology,Guilin 541004,China;School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China;GUET-Nanning E-Tech Research Institute Co.,Ltd.,Nanning 530031,China;Global Unichip Co.,Ltd.,Nanjing 211500,China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004 [2]桂林电子科技大学信息与通信学院,广西桂林541004 [3]南宁桂电电子科技研究院有限公司,南宁530031 [4]创意电子股份有限公司,南京211500

出　　处：《桂林电子科技大学学报》2024年第4期401-408,共8页Journal of Guilin University of Electronic Technology

基　　金：国家自然科学基金(62061010,62161007);广西科技厅项目(桂科AA20302022,桂科AB21196041,桂科AB22035074,桂科AD22080061);桂林市科技项目(20210222-1);广西高校中青年教师科研基础能力提升项目(2022KY0181);广西精密导航与应用重点实验室开放基金(DH202215,PT22001P)。

摘　　要：静态时序分析是芯片设计的一个重要环节。在22nm工艺下的静态时序分析中,采用传统的OCV方法会导致时序不准确、性能不稳定和设计鲁棒性下降等问题。为了提高时序精确性和缩小设计周期,提出了一种基于22 nm工艺的GNSS导航芯片分析方法,使用ICC2实现布局布线以及PrimeTime工具实现静态时序分析;将遵循正态分布的局部参数替代固定的全局参数,采用参数式片上偏差技术结合路径分析模式进行建模。实验结果表明,参数式片上偏差与路径相结合建模的分析方法相较于先进式片上偏差技术,WNS优化了约56.2%,TNS改善了约82.2%,总违例路径减少了58.7%,节省了高达50.8%的时序分析时间,验证了参数式片上偏差与路径相结合的方法的优越性,降低了悲观度,提高了时序精确性,缩小了设计周期。Static timing analysis holds a crucial position in the realm of chip design.In the static timing analysis under the 22nm pro-cess,adopting the traditional on-chip variation(OCV)method will lead to problems such as inaccurate timing,unstable performance,and decreased design robustness.In order to improve the timing accuracy of the design and shorten its design cycle.An analysis method for a GNSS navigation chip based on 22 nm technology is proposed.The ICC2 tool is employed for layout and routing,while PrimeTime is used for static timing analysis.The design replaces fixed global parameters with local parameters following nor-mal distribution,uses parametric on-chip variation(POCV)technology combined with path-based analysis(PBA)to model.Experi-mental results demonstrate that the method combines parametric on-chip deviation and path modeling.When compared to advanced on-chip deviation technology,it shows significant improvements:the worst negative slack(WNS)is optimized by approximately 56.2%,the total negative slack(TNS)is enhanced by around 82.2%,and the overall violation path count is reduced by 58.7%.This leads to substantial savings in timing analysis time,with an efficiency gain of up to 50.8%.This effectively demonstrates the strengths and weaknesses of the combined approach of POCV and PBA,leading to improved timing accuracy and shortened design cycle.

关 键 词：22nm工艺 静态时序分析 先进式片上偏差 参数式片上偏差 路径分析模式 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]