基于国产FPGA的EEPROM读写控制器设计  

Design of EEPROM Read and Write Controller Based on Domestic FPGA

作　　者：陈燕 甄国涌[2] 储成群[2] 崔杰 CHEN Yan;ZHEN Guoyong;CHU Chengqun;CUI Jie(A Military Representative Office of the Military Representative Bureau in Beijing of the Army Equipment Department,Taiyuan 030009;National Key Laboratory of Electronic Testing Technology,North University of China,Taiyuan 030051)

机构地区：[1]陆军装备部驻北京地区军事代表局某军事代表室,太原030009 [2]中北大学电子测试技术国家重点实验室,太原030051

出　　处：《舰船电子工程》2024年第10期164-169,共6页Ship Electronic Engineering

基　　金：国家自然科学基金青年科学基金项目(编号:62131018)资助。

摘　　要：依据IIC串行通信信号传输规范,设计了一种基于国产FPGA的EEPROM读写控制方案。将国产FPGA芯片PGL50G作为核心控制器件,通过硬件模块和软件模块设计对EEPROM芯片以字节为单位进行数据读写控制。在硬件模块的电路设计上,通过外接2.21 K的上拉电阻实现FPGA与EEPROM的信号连接;在软件模块的逻辑设计上,通过“自顶向下”的设计方式,按模块划分对读写控制所使用的IIC通信协议进行实现。设计完成后,使用Modelsim SE-64 2020.4与Pango Design Suite 2022.2-SP3 Debugger工具对设计的读写控制器进行信号分析和验证,结果表明该设计方法合理,可对EEPROM芯片地址灵活配置并正确的读写数据,具有实际的应用价值。According to the IIC serial communication signal transmission specification,a EEPROM read and write control scheme based on domestic FPGA is designed.Using the domestically produced FPGA chip PGL50G as the core control device,the EEPROM chip is designed with hardware and software modules to control data read and write in bytes.In the circuit design of the hardware module,the signal connection between FPGA and EEPROM is achieved through an external 2.21 K pull-up resistor.In the logic design of software modules,a top-down design approach is adopted to implement the IIC communication protocol used for read and write control according to module division.After the design is completed,signal analysis and verification of the designed read and write controller are carried out using Modelsim SE-64 2020.4 and Pango Design Suite 2022.2-SP3 Debugger tools.The results show that the design method is reasonable,can flexibly configure the EEPROM chip address,and correctly read and write data,which has practical application value.

关 键 词：FPGA 串行通信 IIC PGL50G EEPROM 

分 类 号：TP334.5[自动化与计算机技术—计算机系统结构]