基于高速串行总线的DSP+FPGA架构图像处理系统设计  

Design of image processing system based on high-speed serial buses and DSP+FPGA architecture

作　　者：李佩斌[1] LI Peibin(The First Research Institute of Ministry of Public Security,Beijing 102200,China)

机构地区：[1]公安部第一研究所,北京102200

出　　处：《集成电路与嵌入式系统》2024年第12期45-51,共7页Integrated Circuits and Embedded Systems

摘　　要：采用高性能DSP+FPGA架构可满足嵌入式图像处理系统对大数据量、复杂算法的实时处理需求,传统的DSP+FPGA架构使用并行外部存储器接口作为数据传输接口,走线条数较多,布线难度大,故障点多。采用高速串行总线可解决以上问题,本文提出一种基于高速串行总线的DSP+FPGA架构图像处理系统,采用PCIe总线作为DSP与FPGA之间的图像数据传输通道,SRIO总线作为DSP与DSP之间的数据传输通道,SGMII总线作为DSP与PHY芯片的数据传输通道。高速串行总线使得数据传输率更高,布线更容易,减小了电磁干扰,提高了抗干扰能力。本文设计的系统已在实际场所中部署并稳定运行,验证了设计的可行性和系统的可靠性。The high-performance DSP+FPGA architecture can meet the real-time processing requirements of the embedded image processing system for large amounts of data and complex algorithms.The traditional DSP+FPGA architecture uses the parallel external memory interface as the data transfer interface,with a large number of traces,difficult PCB wiring,and many failure points.The use of high-speed serial buses can solve the above problems.This paper proposes an image processing system based on high-speed serial buses and DSP+FPGA architecture.PCIe bus is used as the image data channel between DSP and FPGA,SRIO bus is used as the link between DSP and DSP,and SGMII bus is used as the data channel between DSP and PHY chip.High-speed serial buses enable faster the data transfer rate,easier layout of the PCB,lower electromagnetic interference,and better noise immunity.The system designed in this paper has been deployed and operated stably in practical locations,which demonstrates that the design is feasible and the system is reliable.

关 键 词：高速串行总线 PCIE DSP FPGA DSP+FPGA架构 

分 类 号：TP391.4[自动化与计算机技术—计算机应用技术]