有效减小FOPLP中芯片偏移量的方法  

Method for Effectively Reducing Chip Offset in FOPLP

作　　者：刘吉康 LIU Jikang(College of Physics and Mechanical and Electrical Engineering,Hubei University of Education,Wuhan 430205,China)

机构地区：[1]湖北第二师范学院物理与机电工程学院,武汉430205

出　　处：《电子与封装》2024年第12期25-31,共7页Electronics & Packaging

摘　　要：塑封制程中的芯片偏移量一直是板级扇出型封装(FOPLP)技术面临的巨大挑战。在介绍现有FOPLP技术工艺的基础上,通过分析塑封制程中产生芯片偏移量的原因,借鉴华天科技的嵌入式硅基扇出(eSiFO)封装技术,提出了3种能有效减小FOPLP中芯片偏移量的方法,即凹槽型塑封结构方法、贯穿型塑封结构方法和光阻围堰型封装结构方法。凹槽型和贯穿型塑封结构方法通过制备带凹槽或贯穿结构的板级塑封样品,将芯片粘贴在凹槽结构或贯穿结构内,再配合真空压膜工艺来达到减小FOPLP中芯片偏移量的目的。光阻围堰型封装结构方法利用光阻在承载板上形成光阻围堰结构,将芯片粘贴在光阻围堰结构内,以达到减小FOPLP中芯片偏移量的目的。Chip offset in the plastic sealing process has always been a huge challenge for panel-level fan-out package(FOPLP)technology.Based on the introduction of the existing FOPLP technology,the causes of chip offset in the plastic sealing process are analyzed,and the embedded silicon fan-out(eSiFO)package technology of Huatian Technology is used for reference.Three feasible methods that can effectively reduce the chip offset in FOPLP are proposed,namely groove type plastic sealing structure method,penetration type plastic sealing structure method,and photoresist cofferdam type package structure method.The groove type plastic sealing structure method and penetration type plastic sealing structure method can reduce the chip offset in FOPLP by preparing the panel-level plastic sealing sample with groove type or penetration type structure,sticking the chip in the groove type or penetration type structure,and then combining with the vacuum film process.The photoresist cofferdam type package structure method uses photoresist to form a photoresist cofferdam structure on the carrier board,and sticks the chip in the photoresist cofferdam structure to reduce the chip offset in FOPLP.

关 键 词：板级扇出型封装 芯片偏移量 塑封制程 eSiFO 

分 类 号：TN305.94[电子电信—物理电子学]