面向通用处理器芯粒架构探索和评估的系统级模拟器  

A System-level Exploration and Evaluation Simulator for chiplet-based CPU

作　　者：张聪武 刘澳 张科[1,2] 常轶松 包云岗[1,2] ZHANG Congwu;LIU Ao;ZHANG Ke;CHANG Yisong;BAO Yungang(State Key Lab of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China;School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049,China;Henan Institute of Advanced Technology,Zhengzhou University,Zhengzhou 450003,China)

机构地区：[1]中国科学院计算技术研究所处理器芯片全国重点实验室,北京100190 [2]中国科学院大学计算机科学与技术学院,北京100049 [3]郑州大学河南先进技术研究院,郑州450003

出　　处：《电子与信息学报》2024年第12期4575-4588,共14页Journal of Electronics & Information Technology

基　　金：中国科学院战略性先导科技专项(XDA0320000,XDA0320300);国家自然科学基金重大项目(62090020)。

摘　　要：随着摩尔定律的逐步失效,芯片制造工艺的提升愈发困难,芯片性能的提升面临“面积墙”问题,chiplet(芯粒)技术开始被广泛采用来解决此问题。然而,面向chiplet引入的架构设计参数,目前的体系结构模拟器面临新的挑战。为了能够探索chiplet架构的特定设计参数,现有工作通常只会为模拟器增加单一的功能,导致其难以用于探索多个参数对chiplet芯片的整体影响。为了能够较为全面地探索和评估chiplet芯片架构,该文基于现有gem5模拟器实现了面向通用处理器芯粒架构探索和评估的系统级模拟器(SEEChiplet)模拟器框架。首先,总结了现在chiplet芯片设计关注的3类设计参数,包括:(1)芯片cache系统设计;(2)封装方式模拟;(3) chiplet间的互连网络。其次,针对上述3类参数:(1)设计并实现了私有末级缓存系统,扩大了cache系统设计空间;(2)修改了gem5已有的全局目录,以适配私有末级缓存(LLC)系统;(3)建模了两种常见的chiplet封装方式以及chiplet间互连网络。最后,该文在SEEChiplet框架中进行了系统级的模拟评估,在被测chiplet架构通用处理器上运行操作系统及PARSEC 3.0基准测试程序,验证了SEEChiplet的功能,证明SEEChiplet可以对chiplet设计空间进行探索和评估。As Moore’s Law comes to an end,it is more and more difficult to improve the chip manufacturing process,and chiplet technology has been widely adopted to improve the chip performance.However,new design parameters introduced into the chiplet architecture pose significant challenges to the computer architecture simulator.To fully support exploration and evaluation of chiplet architecture,System-level Exploration and Evaluation simulator for Chiplet(SEEChiplet),a framework based on gem5 simulator,is developed in this paper.Firstly,three design parameters concerned about chiplet chip design are summarized in this paper,including:(1)chiplet cache system design;(2)Packaging simulation;(3)Interconnection networks between chiplet.Secondly,in view of the above three design parameters,in this paper:(1)a new private last level cache system is designed and implemented to expand the cache system design space;(2)existing gem5 global directory is modified to adapt to new private Last Level Cache(LLC)system;(3)two common packaging methods of chiplet and inter-chiplet network are modeled.Finally,a chiplet-based processor is simulated with PARSEC 3.0 benchmark program running on it,which proves that SEEChiplet can explore and evaluate the design space of chiplet.

关 键 词：芯粒 设计空间探索 体系结构模拟器 缓存系统 

分 类 号：TN4[电子电信—微电子学与固体电子学] TN319