一种UHF RFID标签低功耗物理设计与实现  

Physical Design and Realization of a Low-power UHF RFID Tag

作　　者：王成龙[1] 张万荣 万培元[1] 祝雪菲 王树甫 

机构地区：[1]北京工业大学北京市嵌入式系统重点实验室,北京100124 [2]斯凯瑞利(北京)科技有限公司,北京100085

出　　处：《固体电子学研究与进展》2015年第3期253-258,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(60776051;61006044;61006059);北京市科技计划项目(Z141100006014032);北京市自然基金资助项目(4142007;4143059);北京市教委科技发展计划项目(KM200910005001);北京市优秀跨世纪人才基金资助项目(67002013200301)

摘　　要：针对超高频射频识别(UHF RFID)标签低功耗、低成本的要求,本文基于EPC Class-1 Generation-2/ISO18000-6C协议,提出一种采用多电源电压域、新型时钟树综合与局部时钟树构建的物理设计方法。该方法结合广泛应用的门控时钟技术,对芯片时钟网络进行优化设计。与传统方法相比,该方法大幅度减少时钟缓冲器插入数量,有效降低时钟网络功耗,减小芯片面积。最终验证结果表明,所设计的标签符合协议,芯片总面积为0.72mm2,其中数字逻辑面积0.15mm2,平均功耗为9.76μW,在TSMC 0.18μm的标准CMOS工艺下实现流片。In order to meet the requirements of the low power consumption and low cost of UHF RFID tag,aphysical design with multi-supply multi-voltage(MSMV),new clock tree synthesis and local clock tree construction was proposed in this paper based on EPC Class-1Generation-2/ISO18000-6Cagreement.This method employing the clock gating technology was used to optimize the chip clock network.Compared with the traditional method,the number of clock buffer insertion was greatly reduced,while the power consumption of the clock network and the chip area were decreased.The verified results show that the tag conforms to the requirements of agreement,with the total chip area of 0.72mm2,digital logic area of 0.15mm2,and the average power consumption of 9.76μW.Finally,the chip was taped out with the standard CMOS process of TSMC 0.18μm.

关 键 词：射频识别 低功耗 多电源电压 时钟树综合 物理设计 

分 类 号：TP391.44[自动化与计算机技术—计算机应用技术]