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机构地区:[1]石家庄铁道大学四方学院,石家庄051132 [2]石家庄学院,石家庄050035 [3]石家庄市裕华区教育局,石家庄050000
出 处:《固体电子学研究与进展》2015年第3期272-276,共5页Research & Progress of SSE
基 金:河北省科学计划资助项目(13220344);石家庄市科研与发展课题(11113451)
摘 要:提出了一种新型图形化三埋层SOI LDMOS高压器件结构,利用阶梯埋层和埋层1窗口将大量空穴束缚于埋层1和埋层2的上表面,提高了两者的纵向电场,并将器件的耐压从常规结构的470V提高到了805V。因为埋层2的厚度和介电常数对器件耐压无影响,所以埋层2可选取较薄且热导率较高的绝缘材料,埋层2采用热导率为40 W/(m·K)的绝缘介质比采用SiO2最高结温降低了12K。新型器件结构达到兼顾提高耐压和降低自热效应的效果。A novel high voltage SOI LDMOS with graphical three buried layer(GTBL SOI LDMOS)was introduced.The electric field strengths of buried layer 1and buried layer 2were increased obviously,because the holes were collected on the top interfaces of buried layer 1and buried layer 2.The breakdown voltage(BV)of GTBL SOI LDMOS was increased from 470 Vof conventional SOI to 805 V.As the thickness and dielectric constant of buried layer 2had little effect on the BVof GTBL SOI LDMOS,the thin materials with high thermal conductivity was recommended.A reduction of 12 Kof the maximal junction temperature of GTBL SOI LDMOS with insulator whose thermal conductivity was 40 W/(m·K)for the buried layer was obtained,compared with that of SiO2 for the buried layer 2.As a result,the novel device can not only improve the BV,but also reduce self-heating effect.
分 类 号:TN386[电子电信—物理电子学]
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