一种带有自适应鉴相型电压电流转换模块的40 Gbit/s PAM4时钟数据恢复电路设计  

A 40 Gbit/s PAM4 Clock Data Recovery Circuit with Adaptive PD_V2I Module

作　　者：王看民 徐卫林[1] 韦雪明[2] 韦保林[2] 李海鸥[2] 谢镭僮 刘程斌 WANG Kanmin;XU Weilin;WEI Xueming;WEI Baolin;LI Haiou;XIE Leitong;LIU Chengbin(Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin University of Electronic Technology,Guilin Guangxi 541004,China;Key Laboratory for Microelectronic Devices and Integrated Circuits of College and Universities in Guangxi,Guilin University of Electronic Technology,Guilin Guangxi 541004,China;Hunan Goke Microelectronics Co.,Ltd.,Changsha Hu'nan 410131,China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004 [2]桂林电子科技大学广西高校微电子器件与集成电路重点实验室,广西桂林541004 [3]湖南国科微电子股份有限公司,湖南长沙410131

出　　处：《电子器件》2024年第6期1485-1492,共8页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(62064002,62164003);广西精密导航技术与应用重点实验室基金(DH202212);广西创新研究团队项目(2018GXNSFGA281004);桂林电子科技大学研究生教育创新计划资助项目(2022YCX0334)。

摘　　要：为了降低传统Bang-Bang型四脉冲幅度调制(PAM4)时钟数据恢复电路(CDR)在锁定后由于非线性引入的抖动,提出了一种自适应鉴相型电压电流转换模块,在基于锁相环的四分之一速率架构下,通过对数据边沿采样模块并行输出的9组鉴相信息进行求和,动态输出多级电流,在未锁定阶段加大电流,加快锁定速度;在锁定阶段减小电流,降低抖动。40 nm CMOS工艺下的设计仿真结果表明,提出的PAM4 CDR在串行数据速率40 Gbit/s下工作时恢复时钟峰峰抖动为1.1 ps,与传统1/4速率架构PAM4 CDR相比具有锁定快抖动小的优点。In order to alleviate the jitter introduced by the nonlinearity of the traditional Bang-Bang four-pulse amplitude modulation(PAM4)clock data recovery(CDR)circuit after locking,an adaptive PD_V2I module is proposed.Under the quarter rate architecture,by summing the 9 sets of phase detection information output in parallel by the data edge sampling module,the multi-level current is dynamically output,and the current is increased in the unlocked phase to speed up the locking speed;the current is reduced in the locked phase to reduce jitter.The circuit is designed in 40 nm CMOS process.The simulation results show that the four-pulse amplitude modulation clock data recovery circuit works at a serial data rate of 40 Gbit/s,and the peak-to-peak jitter of the recovered clock is 1.1 ps.Compared with the traditional four-pulse amplitude modulation clock data recovery circuit,it has the advantages of fast locking and small jitter.

关 键 词：四脉冲幅度调制 时钟数据恢复 四分之一速率 锁相环 自适应 

分 类 号：TN432[电子电信—微电子学与固体电子学]