采用交叉耦合误差放大器的低压高增益LDO设计  

Low-Voltage High-Gain LDO Design Using Cross-Coupled Error Amplifier

作　　者：张锦辉 朱春茂 张霖 ZHANG Jinhui;ZHU Chunmao;ZHANG Lin(School of Electronic,Electrical Engineering and Physics,Fujian University of Technology,Fuzhou 350100,China;National Demonstration Center for Experimental Electronic Information and Electrical Technology Education,Fujian University of Technology,Fuzhou 350100,China)

机构地区：[1]福建理工大学电子电气与物理学院,福州350100 [2]福建理工大学电子信息与电气技术国家级实验教学示范中心,福州350100

出　　处：《电子与封装》2025年第1期52-58,共7页Electronics & Packaging

基　　金：福建理工大学科研启动基金(GY-Z21066);福建省教育厅项目(FBJG20220019)。

摘　　要：设计了一种低输入电压、高增益的LDO,其误差放大器采用交叉耦合结构来增大环路增益,并通过密勒电容和调零电阻的串联引入1个左半平面的零点,确保该电路的频率响应环路稳定性。采用0.35μm标准CMOS工艺进行仿真,输入电压为1.5 V、负载最大电流为100 mA。仿真结果表明,构建的LDO可以将输出电压稳定在1.2 V,环路的低频增益在轻载的情况下高达122 dB,芯片面积为0.196 mm2,且相位裕度在重载情况下亦能做到大于58°,静态电流为21.2μA。由于交叉耦合误差放大器的使用,电路的精度得到很大提高,负载调整率可以达到0.007%,所设计的LDO有较高的应用价值。An LDO with a low input voltage and a high gain is designed.The error amplifier adopts a cross-coupled structure to increase the loop gain,and a left half-plane zero is introduced by the series connection of a Miller capacitor and a nulling resistor to ensure the frequency response loop stability of the circuit.The 0.35μm standard CMOS process is used for simulation with an input voltage of 1.5 V and a maximum load current of 100 mA.Simulation results show that the constructed LDO can stabilize the output voltage at 1.2 V,and the low-frequency gain of the loop is as high as 122 dB under the light load,with a chip area of 0.196 mm2.The phase margin under the heavy load can also be greater than 58°,with a quiescent current of 21.2μA.Due to the employment of the cross-coupled error amplifier,the circuit's accuracy is greatly improved,and the load regulation can reach 0.007%.The designed LDO is of great value in regard of application.

关 键 词：低压 交叉耦合 LDO 跨导运算放大器 

分 类 号：TN432[电子电信—微电子学与固体电子学]