面向Duobinary信号的时钟恢复电路研究与设计  

Research and design of clock recovery circuit for Duobinary signal

作　　者：袁梁勇 齐星云[1] 吕方旭 罗章[1] 黄恒 张庚 王文晨 李萌 赖明澈[1] YUAN Liangyong;QI Xingyun;LU Fangxu;LUO Zhang;HUANG Heng;ZHANG Geng;WANG Wenchen;LI Meng;LAI Mingche(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2025年第1期27-34,共8页Computer Engineering & Science

基　　金：国家重点研发计划(2021YFB2206600)。

摘　　要：高速串行接口是高性能计算机系统中芯片之间的互连核心,针对高速串行通信所需高带宽问题,在Candence平台上基于Verilog-AMS完成56 Gbps Duobinary信号时钟数据恢复电路设计与仿真,多电平传输可以减小对带宽的需求。基于相位差值器(PI)设计时钟数据恢复(CDR)电路,以Bang-Bang鉴相器的鉴相结果作为鉴相依据,采用数字信号处理(DSP)算法处理鉴相结果,其包括投票算法、滤波算法以及相位控制码转换算法。数字算法降低了电路设计的复杂度,便于调节环路增益,提高了系统的稳定性,降低环路延迟。仿真结果表明,该CDR电路可以进行相差和100 PPM频差的追踪。对输入数据分别增加0.25 UI正弦抖动,环路带宽为23 MHz,当抖动频率未超过环路带宽时,系统能够跟踪正弦抖动。抖动容限满足CEI-56G协议规范。High-speed serial interfaces serve as the interconnect core between chips in high performance computer systems.Addressing the high bandwidth requirements for high-speed serial communication,the design and simulation of a 56 Gbps Duobinary signal clock and data recovery(CDR)circuit were completed based on Verilog-AMS on the Candence platform.Multi-level transmission can reduce the demand for bandwidth.The CDR circuit was designed using a phase interpolator(PI),with the phase detection results from a Bang-Bang phase detector serving as the basis for phase discrimination.Digital signal processing(DSP)algorithms,including a voting algorithm,filtering algorithm,and phase control code conversion algorithm,were employed to process the phase detection results.The digital algorithms reduced the complexity of the circuit design,facilitated the adjustment of loop gain,improved system stability,and decreased loop delay.Simulation results demonstrate that the CDR circuit can track phase differences and frequency offsets of 100 PPM.By adding a 0.25 UI sinusoidal jitter to the input data,with a loop bandwidth of 23 MHz,the system can track the sinusoidal jitter when the jitter frequency does not exceed the loop bandwidth.The jitter tolerance meets the specifications of the CEI-56G protocol.

关 键 词：时钟数据恢复 Duobinary信号 Bang-Bang鉴相器 数字信号处理算法 正弦抖动 

分 类 号：TP393.03[自动化与计算机技术—计算机应用技术]