量子电压芯片制备中的介质层平坦化  

Interlayer Dielectric Planarization in Quantum Voltage Chip Fabrication

作　　者：曹樾 徐思思 钟源[2] 李劲劲[2] 钟青[2] 曹文会[2] 蔡晋辉[1] CAO Yue;XU Sisi;ZHONG Yuan;LI Jinjin;ZHONG Qing;CAO Wenhui;CAI Jinhui(China Jiliang University,Hangzhou,Zhejiang 310018,China;National Institute of Metrology,Beijing 100029,China)

机构地区：[1]中国计量大学,浙江杭州310018 [2]中国计量科学研究院,北京100029

出　　处：《计量学报》2025年第1期106-111,共6页Acta Metrologica Sinica

基　　金：国家重点研发计划(2022YFF0608301);国家自然科学基金(61971471)。

摘　　要：在制造量子电压芯片时,使用二氧化硅薄膜作为层间介质层(IDL)可以实现约瑟夫森结的电气连接。通常二氧化硅是保形沉积的,后续的铌线层容易在直角台阶附近形成晶界裂纹。考虑到光刻和芯片高低温循环可靠性,需要对IDL进行平坦化处理。相对其他平坦化方案,牺牲层回刻的方法工艺步骤简单,适用于小批量的研究工作。具体步骤为:在IDL上旋涂覆盖厚光刻胶层填充图形中的沟壑并形成平坦的界面;然后采用反应离子束刻蚀等速去除光刻胶和SiO_(2),整体上完全刻蚀到SiO_(2)层后即可得到平坦的介质层表面,消除绝缘层台阶。其中光刻胶和SiO_(2)的等速刻蚀通过调节氧气流量与射频功率来实现。在回刻过程中使用终点探测系统实时监控平坦化状态,根据反射光强变化曲线来判断刻蚀深度,并决定何时停止这一过程。采用以上方法成功在结区上方形成厚度适宜、表面平坦的介质层。将牺牲层回刻法应用于芯片的制备,得到了没有裂纹的铌线层。芯片具有良好的直流特性曲线,有效提升了芯片的高低温循环可靠性。In the fabrication of quantum voltage chips,thin films of silicon dioxide are used as interlayer dielectric layers(IDL)to realize the electrical connections of Josephson junctions.However,typically silicon dioxide film is conformally deposited and subsequent niobium wire layers are prone to form grain boundary cracks near the rectangular steps.Planarization of the IDL is necessary for lithography and chip reliability considerations.Compared to other planarization schemes,the etch-back method has simple process steps and is suited for research work.A thick photoresist layer is spin-coated over the IDL to fill the trenches in the pattern and form a planar interface.Then,a reactive ion etching system is used to etch back the photoresist and SiO_(2) at the same speed.A planar dielectric layer surface can be obtained when the photoresist layer is etched up.The same etching rate of photoresist and SiO_(2) is realized by adjusting the oxygen flow and RF power.Additionally,in order to monitor the planarization status,an end-point detection system is applied in the etch-back process.Based on the light intensity reflected from the substrate surface,one can determine the etching depth and decide when to stop the process.The above method was successfully used to form a planarized dielectric layer above the junction area.By applying this etch-back method in the chip fabrication process,no crack is formed in the niobium wiring layer,and good I-V curves are obtained for the chip.The reliability of the chip is effectively improved.

关 键 词：电学计量 量子电压芯片 平坦化 回刻 终点探测 约瑟夫森结 

分 类 号：TB971[一般工业技术—计量学]