一种12位100 kS/sR-C混合型SAR ADC  

A 12 bit 100 kS/s R-C hybrid SAR ADC

作　　者：邹贤婧 吴逸飞 万美琳 ZOU Xianjing;WU Yifei;WAN Meilin(School of Microelectronics,Hubei University,Wuhan 430062,China)

机构地区：[1]湖北大学微电子学院,湖北武汉430062

出　　处：《微电子学与计算机》2025年第1期75-83,共9页Microelectronics & Computer

基　　金：国家自然科学基金(62174050)。

摘　　要：提出了一种单调性优异的R-C混合型SAR ADC。其高八位DAC采用电阻型结构,低四位DAC采用电容型结构,通过高八位DAC中电阻串分压结构将基准电压进行等分,选择与输入采样信号最接近的电压,再将该电压输入至低四位电容型DAC中进行电荷重分配过程,最终实现12位DAC输出。为减小工艺失配引起的误差,此低四位CDAC仅包括比例为15C:C的两个电容,其中15C电容接高八位电阻型DAC的输出电压,该电压受高八位控制信号D[11:4]影响,而C电容所连接的电压值也由高八位电阻型DAC输出,该电压受高八位与低四位控制信号D[11:0]影响。由于低四位电容型DAC的输入电压只与高八位电阻型DAC输出电压相关,同时电阻型DAC具有较好的单调性,因此只需保证低四位DAC中15C和C之间匹配良好,就可以获得优异的单调性。同时,该SAR ADC兼容差分输入和单端输入模式。基于华虹GRACE 0.11μm CMOS工艺进行设计和实现后,仿真结果表明:在各个工艺角、温度情况下,该SAR ADC的DNL、INL均小于±1 LSB,典型情况下ENOB为11.4 bit,最大功耗不超过600μA,能够适用于中高精度、低成本的应用需求。An R-C hybrid SAR ADC with excellent monotonicity is proposed,in which the high-eight-bit digital-to-analog converter adopts a resistive structure,and the low-four-bit DAC adopts a capacitive structure.The reference voltage is divided equally through the resistive divider in the high-eight-bit DAC,and the voltage closest to the input sampling signal is selected as the output of high-eight-bit DAC.Then the result is input to the low-four-bit capacitive DAC for charge redistribution process,and finally the 12-bit DAC output is realized.In order to reduce the error caused by process mismatch,the lower-four-bit capacitive DAC consists of only two capacitors with a ratio of 15C:C.The 15C-capacitor is connected to the output of the high-eight-bit resistive DAC,which is affected by the high-eight-bit control signal D[11:4].The voltage connected to the C-capacitor is also output by the high-eight-bit resistive DAC,which is affected by both the high-eight-bit and the low-four-bit control signal D[11:0].Since the input voltage of the low-four-bit capacitive DAC is only correlated with the output voltage of the high-eight-bit resistive DAC,and the resistive DAC has good monotonicity,it is only necessary to ensure that the 15C-capacitor and C-capacitor in the low-four-bit DAC are well matched to achieve good monotonicity.At the same time,the ADC is compatible with both differential and single-ended input modes.The proposed ADC is implemented using GRACE 0.11μm CMOS process,the post-simulation results show that the differential nonlinearity and integral nonlinearity are both less than±1 LSB in all the process corners and temperature environments.The ENOB is 11.4 bit under typical conditions,and the maximum power consumption is smaller than 600μA,which can be suitable for medium-and high-precision and low-cost applications.

关 键 词：SAR ADC 比较器 混合型DAC 单调性 采样模式 

分 类 号：TN432[电子电信—微电子学与固体电子学]