基于高速安全存储SoC芯片的PCIe集成验证  

PCIe integration verification based on high-speed secure storage SoC chip

作　　者：商建东 闫法瑞 于哲 郭恒亮[1,2] SHANG Jiandong;YAN Farui;YU Zhe;GUO Hengliang(School of Computer and Artificial Intelligence,Zhengzhou University,Zhengzhou 450001,China;National Supercomputing Center in Zhengzhou,Zhengzhou University,Zhengzhou 450001,China)

机构地区：[1]郑州大学计算机与人工智能学院,河南郑州450001 [2]郑州大学国家超级计算郑州中心,河南郑州450001

出　　处：《微电子学与计算机》2025年第1期84-91,共8页Microelectronics & Computer

基　　金：河南省重大科技专项(221100210600)。

摘　　要：高速串行总线(Peripheral Component Interconnect express,PCIe)是一种计算机高速串行扩展总线协议,能够提供点对点高带宽传输。自研高速安全存储系统级芯片(System on Chip,SoC)在高速传输的需求之上提出了对PCIe接口需求。为验证自研高速安全存储SoC芯片集成PCIe模块满足设计应用需求,在对高速安全存储SoC芯片架构以及PCIe EP模块进行详细说明基础上,基于UVM通用验证方法学与PCIe VIP应用,搭建了高速安全存储SoC的PCIe集成验证平台。可配置的PCIe VIP验证平台方案简化了集成及验证工作,减少了验证所需的思考时间,解决了数据传输验证中针对性交互场景验证难题,缩短了验证平台的开发时间。通过对PCIe EP模块的功能分析,设计了相关寄存器配置、片内缓存数据交互等仿真测试用例。针对DMA传输功能验证难题则提出通过监测中断次数并联合波形以及日志来确认功能完整。最后结合仿真波形及相关日志记录结果分析,验证了存储SoC集成的PCIe模块传输相关功能正确性,数据传输涉及相关寄存器覆盖率达到了85%以上。该方案验证平台及测试用例适用于之后接口升级需求的验证工作中。PCIe is a high-speed serial expansion bus protocol for computers,which can provide point-to-point high bandwidth transmission.The self-developed high-speed secure storage SoC has proposed requirements for the PCIe interface on top of the high-speed transmission requirements.To verify that the integration of the self-developed high-speed secure storage SoC chip with the PCIe module meets the design application requirements,this article provides a detailed explanation of the high-speed secure storage SoC chip architecture and PCIe EP module,and based on the UVM universal verification methodology and PCIe VIP application,builds a high-speed secure storage SoC PCIe integration verification platform.The configurable PCIe VIP verification platform solution simplifies integration and verification work,reduces the thinking time required for verification,solves the problem of targeted interaction scenario verification in data transmission verification,and shortens the development time of the verification platform.Through functional analysis of the PCIe EP module,simulation test cases such as register configuration and on-chip cache data interaction are designed.In response to the challenge of verifying the DMA transmission function,it is proposed to confirm the completeness of the function by monitoring the number of interrupts and combining waveforms and logs.Finally,combined with the analysis of simulation waveforms and related log records,the correctness of the transmission related functions of the PCIe module integrated with SoC storage is verified.The coverage rate of the relevant registers involved in data transmission reached over 85%,meeting the expected transmission related functional requirements in the design.The verification platform and test cases of this scheme are applicable to the verification work of interface upgrade requirements in the future.

关 键 词：集成验证 系统级芯片 高速串行总线 通用验证方法学 验证知识产权 

分 类 号：TN4[电子电信—微电子学与固体电子学]