基于Early Clock Flow方式的时钟树综合物理设计  

Physical Design of Clock Tree Synthesis Based on the Early Clock Flow Method

作　　者：杨沛 邹文英 陈柱江 李小强 YANG Pei;ZOU Wenying;CHEN Zhujiang;LI Xiaoqiang(CETC No.58 Research Institute,Jiangsu 214072,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏214072

出　　处：《集成电路应用》2024年第9期1-3,共3页Application of IC

摘　　要：阐述时钟树综合作为芯片后端物理设计的核心步骤,成为制约芯片设计技术发展的关键。基于业界主流设计工具Innovus软件的早期时钟流程Early Clock Flow,改进设计流程,优化时钟树综合结果。与传统时钟树综合对比,时钟单元数量减少3.2%,走线长度减少1.5%,时钟树功耗减少3.7%。特别是时序结果大幅改善,芯片拥塞面积减少32%,设计周期缩短15%,节省了设计成本。This paper expounds that clock tree synthesis,as the critical procedure of the backend physical IC design,has become the key to the develop of IC design technology.Based on the Early Clock Flow,thefunctionof the mainstream EDAtoolInnovus,the IC design flow was improved and the results of CTS were optimized.Compared to the traditional CTS method,the count of the clock cells was reduced by 3.2%,the wire length of the clock tree was decreased by 1.5%,and the power consumption of the clock tree was reduced by 3.7%.Particularly,the timing results were improved greatly,the congestion area was decreased by 32%and the design cycle was shortened by 15%.

关 键 词：电路设计 早期时钟 时钟树综合(CTS) useful skew 物理设计 后端设计 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN431.2