基于FPGA的多路SGMII接口以太网设计与测试  

The design and test of Ethernet with multiple SGMII based on FPGA

作　　者：付强 乔辉 杨飞虎 曹拴住 张竞飞 Fu Qiang;Qiao Hui;Yang Feihu;Cao Shuanzhu;Zhang Jingfei(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子技术应用》2025年第2期75-80,共6页Application of Electronic Technique

摘　　要：嵌入式处理器受功耗、尺寸、成本限制,一般集成1个或2个以太网控制器,不能满足某些特定现场对多路以太网数据同时传输的需求。提出一种基于现场可编程门阵列(FPGA)的以太网设计,利用FPGA高速、并行处理优势,集成的串行/解串器(SerDes)资源情况,扩展出多路以太网接口进行数据同时收发。与外部物理层(PHY)芯片通信采用串行以太网(SGMII)接口,可以有效减少印制线路板(PCB)尺寸和布线数量。提出一种针对底层链路传输可靠性的多级测试方法,最终通过上板调试验证,12路以太网接口在1000 Mb/s速率下传输稳定、数据无误码。Due to power consumption,size,and cost constraints,embedded processors typically integrate one or two Ethernet controllers,which cannot meet the demand for simultaneous transmission of multiple Ethernet data streams in certain specific field applications.This paper proposes an Ethernet design based on Field-Programmable Gate Array(FPGA),leveraging the high-speed and parallel processing advantages of FPGA,and the integrated Serializer/Deserializer(SerDes)resources to extend multiple Ethernet interfaces for simultaneous data transmission and reception.Communication with external PHY chips uses the Serial Gigabit Media Independent interface(SGMII),which can effectively reduce PCB size and wiring complexity.A multi-level testing method for the reliability of the underlying link transmission is proposed.Finally,through on-board debugging and verification,the 12 Ethernet interfaces achieve stable transmission at 1000 Mb/s with no data errors.

关 键 词：FPGA SGMII 以太网 PHY 

分 类 号：TN919.8[电子电信—通信与信息系统]