一种适用于高速动态比较器的失调电压校正技术  

An offset voltage calibration technique for high speed dynamic comparator

作　　者：高亮 江先阳[1,2] GAO Liang;JIANG Xianyang(School of Physics and Technology,Wuhan University,Wuhan 430072,China;National Physics Experimental Teaching Demonstration Center,Wuhan University,Wuhan 430072,China)

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072 [2]武汉大学物理国家级实验教学示范中心,湖北武汉430072

出　　处：《电子设计工程》2025年第5期90-95,共6页Electronic Design Engineering

摘　　要：比较器是模数转换器中的重要模块,高速高精度既是比较器设计的重点,也是设计的难点。文中提出了一种基于电荷泵控制的失调电压消除技术,在满足比较器高速性能的同时,有效降低了失调电压,提高了比较器的精度。这项技术在时钟路径中引入时间误差,消除了传统自归零技术受限于电容阵列精度与建立时间误差的问题,解决了在信号路径中插入非平衡负载这一方案降低比较器速度的问题。该方案的核心版图面积为0.017 mm^(2),周期性交流仿真结果显示该高速动态比较器具有1.6 GHz的高带宽,输入参考失调电压在校正后相比于校正前消除了93.9%。Comparator plays an important role in analog-to-digital converters,whose speed and precision is crucial but difficult to improve.Aiming to attack such problems,a novel offset voltage calibration technique based on charge pump is proposed.The technique takes advantage of time error in clock control path,surpasses traditional auto-zero technologies as they are limited by the precision of capacitor array and settling time,and further eliminates comparator speed reduction caused by an unbalanced load insertion in signal path.The core area of this scheme is 0.017 mm^(2).Periodic AC simulation results demonstrate that the proposed high-speed dynamic comparator achieves a high bandwidth of 1.6 GHz,and the input reference offset voltage decreases by 93.9%after correction compared to state-of-the-art counterparts.

关 键 词：动态比较器 输入失调电压前台校正 高速 压控电容 

分 类 号：TN47[电子电信—微电子学与固体电子学]