一种用于高性能FPGA的多功能I/O电路  

A Multi-Functional I/O Circuit for High Performance FPGA

作　　者：罗旸[1] 刘波 曹正州[1] 谢达[1] 张艳飞[1] 单悦尔[1] Luo Yang;Liu Bo;Cao Zhengzhou;Xie Da;Zhang Yanfei;Shan Yueer(The 58^(th)Research Institute,CETC,Wuxi 214035,China;China Aerospace Newsky Technology Co.,Ltd.,Wuxi 214062,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035 [2]航天新气象科技有限公司,江苏无锡214062

出　　处：《半导体技术》2025年第3期265-272,共8页Semiconductor Technology

基　　金：国家自然科学基金面上项目(62174150);江苏省自然科学基金面上项目(BK20211040,BK20211041)。

摘　　要：为了满足等效系统门数为亿门级现场可编程门阵列(FPGA)的高速率、多功能数据传输需求,设计了一种用于高性能FPGA的多功能输入输出(I/O)电路,工作电压为0.95 V,单个I/O电路的最高数据传输速率为2 Gbit/s。通过在输入逻辑电路中设计同一边沿流水技术的双倍数据速率(DDR)电路,可以使数据不仅能在相同的时钟沿输出,而且能在同一个时钟周期输出。通过分级采样结合时钟分频和偏移技术,仅需4个时钟周期即可完成8∶1数据的转换。另外,该I/O电路还可以对数据输入输出的延时进行调节,采用粗调和细调相结合的方式,共提供512个延时抽头,并且延时的分辨率达到4 ps。仿真和实测结果表明,该多功能I/O电路能为高性能FPGA提供灵活、多协议的高速数据传输功能。In order to meet the requirements of high rate and multi-function data transmission of field programmable gate array(FPGA)withequivalent systemgatecount of 100million,amulti-function input output(I/O)circuit for high performance FPGA was designed.The operating voltage was 0.95 V,and the maximum data transmission rate of a single I/0 circuit was 2 Gbit/s.By designing a double data rate(DDR)circuit with the same edge pipelining technology in the input logic circuit,the data can be output not only on the same clock edge,but also in the same clock cycle.By using hierar-chical sampling combined with clock frequency division and offset technology,only four CLKS were needed to complete the 8:1 data conversion.In addition,the delay of data input and output could be adjusted by the I/0 circuit.By combining coarse adjustment and fine adjustment,a total of 512 delay taps were provided and the delay resolution reached 4 ps.The simulation and measurement results show that the multi-function I/O circuit can provide flexible and multi-protocol high-speed data transmission function for the high performance FPGA.

关 键 词：现场可编程门阵列(FPGA) 输入输出(I/O)电路 多电平标准 双倍数据速率(DDR) 串并转换器(SerDes) 

分 类 号：TN79[电子电信—电路与系统]