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作 者:王英骐 王嘉文 蒯杨 郭润楠 陶洪琪[1] Wang Yingqi;Wang Jiawen;Kuai Yang;Guo Runnan;Tao Hongqi(Nanjing Electronic Devices Institute,Nanjing 210016,China;School of Information and Engineering,Southeast University,Nanjing 210096,China)
机构地区:[1]南京电子器件研究所,江苏南京210016 [2]东南大学信息科学与工程学院,江苏南京210096
出 处:《电子技术应用》2025年第4期84-90,共7页Application of Electronic Technique
摘 要:为满足通信系统发展对高性能硅基低噪声放大器的需要,提出了一种跨导增强双路噪声抵消电路拓扑,能对晶体管噪声进行抵消,以实现良好的噪声性能。共栅路径中引入的跨导增强结构进一步改善了增益与噪声性能。基于以上拓扑设计了一款K波段低噪声放大器,由共栅与共源两条路径组成,两者互为反馈支路,通过两路合成实现双路的噪声抵消。电路采用90 nm CMOS SOI工艺设计,芯片核心尺寸为500μm×280μm。仿真结果表明,在17~22GHz频带内实现了1.61~1.87dB的噪声系数和15.8dB的峰值增益,1dB压缩点输入功率为-4.3dBm,体现了较好的噪声性能与线性增益。To meet the demand for high-performance silicon-based low noise amplifier(LNA)with the development of communication systems,a gm-boost dual path noise-canceling circuit topology is proposed,which can reduce transistor noise and achieve low noise figure(NF).A gm-boost structure is introduced in the common-gate path to further improve the gain and noise performance.A K-band LNA is designed based on the topology mentioned above,consisting of two paths:a common-gate path and a common-source path,each of which acts as feedback branch of the other.Two paths are synthesized to achieve noise cancellation.The LNA is designed under a 90 nm CMOS SOI process,with a chip core size of 500μm×280μm.The simulation results show that a NF of 1.61~1.87 dB and a peak gain of 15.8 dB are achieved in 17~22 GHz.The input power with 1 dB gain compression is-4.3 dBm,demonstrating good noise and linear gain performance.
分 类 号:TN432[电子电信—微电子学与固体电子学]
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