基于瞬态漏源电流变化的SiC MOSFET陷阱表征  

Characterization of SiC MOSFET Traps Based on Transient Drain-Source Current Variations

作　　者：高博文 杜颖晨 张亚民[1] Gao Bowen;Du Yingchen;Zhang Yamin(School of Information Science and Technology,Beijing University of Technology,Bejing 100124,China)

机构地区：[1]北京工业大学信息科学技术学院,北京100124

出　　处：《半导体技术》2025年第5期459-467,共9页Semiconductor Technology

基　　金：国家自然科学基金重点项目(62334002);国家自然科学基金面上项目(62074009);北京市自然科学基金-小米创新联合基金(L233023)。

摘　　要：SiC MOSFET栅极氧化物附近存在的陷阱缺陷造成其在高温高压场景下出现许多可靠性问题。提出了完整的基于瞬态电流法的陷阱表征方案,结合贝叶斯迭代反卷积算法实现对陷阱位置、时间常数和激活能的表征。基于自建陷阱测试平台在栅极和漏极施加不同组合的电学偏置,表征了微秒量级的两个陷阱,其时间常数分别为2×10^(-5)s和2.5×10^(-4)s,并观察到SiC MOSFET中存在同时受栅源电压和漏源电压影响的陷阱,这种现象在沟槽型器件中尤其显著,根据此特性可以分析陷阱的位置。本研究丰富了陷阱表征的信息,为陷阱的定位和表征提供了新的思路。Trap defects near the gate oxide of SiC MOSFETs cause many reliability problems in high-temperature and high-voltage scenarios.A complete trap characterization scheme based on the transient current method was proposed,which was combined with the Bayesian iteration inverse convolution algorithm to achieve the characterization of the trap locations,time constants and activation energies.Based on the self-constructed trap test platform with different combinations of electrical bias applied to the gate and drain,two traps in the microsecond scale with time constants of 2×10^(-5)s and 2.5×10^(-4)s respectively were characterized.It is also observed that there are traps in SiC MOSFETs that are affected by both gate-source and drain-source voltages,and this phenomenon is especially significant in trench-type devices,and the location of the traps can be analyzed based on this characteristic.This study enriches the information of trap characterization and provides a new idea for the location and characterization of traps.

关 键 词：SiC MOSFET 陷阱表征 瞬态电流法 时间常数谱 贝叶斯迭代反卷积 

分 类 号：TN386.1[电子电信—物理电子学] TN307