一种用于低功耗BIST的多重抑制LFSR结构(英文)  

A Multiple LFSR Inhibiting Structure for Low Power BIST

作　　者：许舸夫[1] 张哲[1] 胡晨[1] 毛武晋[1] 刘锋[1] 

机构地区：[1]东南大学国家专用集成电路系统工程中心,南京210096

出　　处：《电子器件》2002年第4期388-391,共4页Chinese Journal of Electron Devices

摘　　要：本文提出了一种多重抑制的线性反馈移位寄存器 (L FSR)结构来降低内建自测试 (BIST)的功耗。这种结构通过矢量间的距离而不是矢量本身来抑制对测试没有贡献的测试矢量子序列。用来估算功耗的电路内部 WSA(Weighted Switching Activity)平均降低了 80 .3%。此外 ,这种结构的另一个优点是 :随着抑制次数的增加 。In this paper, a multiple LFSR inhibiting structure is proposed to reduce the power consumption during BIST. The structure inhibits the non detecting sub sequences not by the vectors but by the distance numbers between the vectors. The average reduction of the internal WSA, which is used to estimate the power consumption, reaches 80.3%. Furthermore, with the increasing of inhibition times, that the area overhead increases more slowly than other filtering or inhibiting techniques is also an advantage of the proposed structure.

关 键 词：LFSR BIST 多重抑制 距离数 线性反馈移位寄存器 内建自测试 

分 类 号：TP332.11[自动化与计算机技术—计算机系统结构]