测试向量中未确定位对测试功耗优化的影响  

Indefinite Test Bits' Influence on Test Power Optimization

作　　者：骆祖莹[1] 李晓维[2] 洪先龙[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084 [2]中国科学院计算技术研究所,北京100080

出　　处：《微电子学与计算机》2003年第2期52-55,共4页Microelectronics & Computer

基　　金：国家自然科学基金重点项目(90207002);国家863计划项目(2001AA111070)

摘　　要：文章通过调整测试向量中未确定位的数目,来考察测试向量中未确定位对测试功耗优化的影响。ISCAS85和ISCAS89电路集的实验结果表明:无论对于组合电路还是时序电路,随着测试向量中未确定位数目的增加,未优化测试功耗有明显的降低,同时对于本文所考察的三种测试功耗优化方法,它们的优化效果均有明显的改善。其中海明距离优化方法的优化效果改善最大,当未确定位数目增加到90%以上时,可以用海明距离优化方法替代另外两种耗时的优化方法,直接对CMOSVLSI时序电路测试功耗进行优化。In this paper,indefinite test bits' influence on test power optimization has been researched through changing the number of indefinite bits in test patterns.Experiments on IS-CAS85and ISCAS89benchmarks demonstrate the following in-fluences not only for combinational circuits but also for sequence circuits.First,with the increase of indefinite test bits,the un-optimized test power markedly decreases.Second,with the in-crease of indefinite test bits,all optimization effects of three op-timization approaches researched in this paper obviously in-crease.Third,the optimization effect of the Hamming distance approach increases the most among three optimization approach-es.Forth,if the percent of indefinite bits is more than90%of all bits in a test pattern,the Hamming distance approach can re-place the other time-consuming approaches to directly optimize the test power for CMOS VLSI sequential circuits.

关 键 词：功耗 海明距离 集成电路 向量测试 电路功耗 时序电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]