一种基于数据总线的测试结构(英文)  

A Test Architecture Based on Data Bus

作　　者：王澍[1] 毛武晋[1] 陆生礼[1] 

机构地区：[1]东南大学国家专用集成电路工程技术研究中心,南京210096

出　　处：《电子器件》2003年第1期46-51,共6页Chinese Journal of Electron Devices

摘　　要：复用数据总线作为测试传输机构的测试结构可以大大减小可测性设计的面积开销。因此 ,提出了一种针对该结构的测试包设计新方法 :通过对测试包中与测试传输机构相连的测试包单元和相连的测试包单元分别设计 ,使前者设计成可寻址的测试数据缓冲器 ,从而构建了一种复用数据总线作为测试传输机构的新测试结构。由此让该结构具备了硬件开销小 ,测试过程控制简单 。The test architecture reusing data bus as TAM can reduce the silicon area cost for DFT greatly. In this paper, we proposed a novel test wrapper design for this architecture. Treating the wrapper cells connecting to TAM and those not connecting to it differently, we design the TAM cells of a wrapped core into an addressable buffer in test session. Therefore, a novel test architecture reusing data bus as TAM is built up, which causes less silicon area and also has the advantages of easy to control and feasible to achieve parallel test.

关 键 词：嵌入式芯核 测试传输机构 测试包 扫描链 测试矢量 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]