高级综合前的检查和转化  

Check and Transition before High-Level Synthesis

作　　者：孟晗[1] 刁岚松[1] 杨凯[1] 

机构地区：[1]北京理工大学ASIC研究所,北京100081

出　　处：《计算机工程与应用》2003年第9期29-31,共3页Computer Engineering and Applications

基　　金：部委"十五"预研项目

摘　　要：Talent2000中VHDL文件的编译中间结果用于综合和模拟,VHDL是面向模拟的语言,并不是所有的VHDL语句都可以综合,在一个实用化高级综合系统中,除了根据可综合子集检查VHDL源描述之外,还要求可综合VHDL描述具有一定的风格。在进行高级综合前,必须对VHDL文件编译的中间结果进行处理,包括语句可综合性检查、VHDL描述的可综合性风格检查、循环语句展开和子程序内联。该文给出了要求VHDL描述具有可综合性风格的原因,实现了面向高级综合的检查、循环语句的展开和子程序内联。The compiled VHDL intermedia result is used for synthesis and simulation in Talent2000High-level digital system design tool.VHDL orients simulation and not all the VHDL statements can be synthesized.In a practical high-level synthesis system the VHDL description is checked according to synthesizable subset and synthesizable style of the VHDL description is required too.So the VHDL intermedia result must be checked and transformed before high-level synthesis.The methods include synthesizable check,synthesizable style of VHDL description check,loop statements expansion and subroutine-inline.This article provides the reasons for the synthesizable style and realizes the check for high-level synthesis,loop statements expansion and subroutine inline-expansion.

关 键 词：高级综合 VHDL 可综合子集 可综合风格 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]