基于逻辑设计的光纤通信8B/10B编解码方法研究  

Study on 8B/10B Encoding and Decoding Method Based on Logic Analysis for Fiber Communication

作　　者：赵文虎[1] 王志功[1] 费瑞霞[1] 朱恩[1] 吴微[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096

出　　处：《电路与系统学报》2003年第2期48-53,共6页Journal of Circuits and Systems

基　　金：国家863高技术计划基金资助项目(2001AA121074);国家杰出青年科学基金资助项目(69825101)

摘　　要：本文研究了8B/10B编码中的内在相关性,并在此基础上提出一种基于逻辑设计的编、解码方法,以达到简化实现结构,用于大规模集成电路设计的目的。仿真结果证明本方法的逻辑运算量小、速度快、可靠性高。同时根据仿真需要,采用0.25μm CMOS工艺制作了编解码芯片中TSPC结构D触发器,其电路面积仅为200μm2。经测试,芯片的工作频率可从150MHz一直到2.37GHz。在50欧姆负载条件下,2.37GHz时钟的二分频信号的电压峰-峰值为1.58V,信号占空比为49%,相位抖动为4ps rms。该测试结果为采用本方法设计不同速率的超高速编解码芯片奠定了基础。Based on logic analysis, inherent relationship between of 8B/10B code and the encode-and-decoding method is investigated. With optimized logic gates, this method can be applied easily and effectively to high speed and low-power-consumption IC design. For IC realization, TSPC D-type flip-flop as the key circuit has been developed using a standard 0.25μm CMOS technology. The core area of this D-type flip-flop is 200μm2. Under the condition of 50Ω load and binary-frequency-division of 2.37GHz clock, 1.58Vp-p output voltage can be available. The duty cycle ratio of the output voltage is 49% and the phase jitter is 4ps rms. The simulation and test results show that the method not only simplifies the design but also extends its application in different communication systems.

关 键 词：8B/10B码 编码 解码 逻辑运算 集成电路 

分 类 号：TN922.7[电子电信—通信与信息系统]