Viterbi译码器的FPGA实现技术研究  

Technology of implementing Viterbi decoder based on FPGA

作　　者：孙晓岩[1] 付永庆[1] 张文鑫[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001

出　　处：《应用科技》2003年第5期11-13,共3页Applied Science and Technology

摘　　要：提出了一种实现高速并行Viterbi译码器的结构 ,并且将SMDO法[1] 用于幸存路径存储和输出模块部分 .本设计已基于FPGA得以实现 ,获得了译码速度快。A new Viterbi decoder with a high rate and parallel structure was presented. A new survivor memory and decoding output (SMDO) method presented was used to implement the new structure. An FPGA based Viterbi decoder was obtained. On the basis of the results of simulations, its advantages in decoding speed and time delay was shown as well.

关 键 词：VITERBI译码器 FPGA 译码速度 路径度量存储模块 

分 类 号：TN918.3[电子电信—通信与信息系统]