CISC微处理器嵌入式内核的设计  

The Design of an Embedded CISC Microprocessor Core

作　　者：方俊锋[1] 杨银堂[1] 

机构地区：[1]西安电子科技大学微电子所,陕西西安710071

出　　处：《微电子学》2003年第4期355-357,361,共4页Microelectronics

摘　　要：　设计了与80C51兼容的微处理器嵌入式内核,用Cadence进行了仿真验证,建立了模型库。仿真结果表明,电路时序特性满足80C51的要求。同时,还对CPU和存储器进行了详细设计。该内核具有速度高、功耗低的特点。An embedded microprocessor core used for ASIC is presented,which is compatible with 80C51 microprocessor The core is verified by using Cadence tools,and model library is established Simulation shows that the timing sequence of the circuit meets the requirement of 80C51 microprocessor The CPU and memory are also designed The device features high speed and low power consumption

关 键 词：CISC微处理器 嵌入式内核 CPU 存储器 80C51单片机 集成电路 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构] TP332[自动化与计算机技术—计算机科学与技术]