在集成电路量产中减少氧化膜CMP(化学机械研磨)的缺陷(英文)  

Defect Reduction of Oxide CMP Process in High Volume Manufacturing

作　　者：张映斌[1] 张世纬 张斐尧 衣冠军 

机构地区：[1]中芯国际,上海201203

出　　处：《电子工业专用设备》2003年第4期21-24,共4页Equipment for Electronic Products Manufacturing

摘　　要：在超大规模集成电路的生产中,减少氧化膜CMP中的各种缺陷一直是工程师们的工作焦点之一。实际上这些缺陷的尺寸、形状、深度等能为我们寻找它们的根源提供许多有益的信息。例如:在肉眼下可见的长、直、深的划伤可能与研磨垫修整器有关;只有在先进的检测设备下才可见的轻微、连续的划伤与与研磨剂有关。对常见缺陷进行分类,并提供一些可见的缺陷产生机制,同时也讨论了如何通过日常检测来监视真正产品上的缺陷。The various mechanisms of defect generation during oxide CMP is always the focus of CMP engineers who work in a mass-production site for VLSI?ULSI devices.The appearance of defect size,shape,depth and pattern on the product wafers provide information on the source of the defects.For example,the long-straight-deep scratches that are visible to human eyes indicate some problems with the conditioner.The chattered marks that only visible under the most advanced inspection tools are usually related to slurry abrasive or debris on the polishing table.In this paper,we will categorize the most frequent types of defectivity post oxide CMP,and provide explanation of the possible mechanisms of defect generation.Certain counter-measure was taken to contain the defect density level,and the result is shown on the daily SPC trend charts.

关 键 词：氧化膜CHP 缺陷 划伤 超大规模集成电路 

分 类 号：TN305.2[电子电信—物理电子学]