流水线设计方法及应用  

Application of the Pipelining Design Method

作　　者：王景存[1] 杨君[1] 郭皓[1] 

机构地区：[1]北京科技大学信息工程学院,北京100083

出　　处：《控制工程》2003年第5期413-415,418,共4页Control Engineering of China

摘　　要：提出了一种流水线设计方法,介绍了VerilogHDL硬件描述语言的特点和Quartus Ⅱ设计软件,阐述了用流水线式的设计思想。以硬件描述语言设计的两种8位全加器为例,在QuartusⅡ设计软件的环境下仿真综合,并下载到实际系统中,模拟系统实际运行的最大频率,将两种设计方法进行比较。结果证明了采用流水线式的设计方法来提高系统的工作速度的可行性,而且此方法在高速系统设计中有良好的应用前景。One pipelining design method is proposed and the characteristics of VerilogHDL language and the design software of Quartus Ⅱ is introduced. It expounds the design idea of the pipelining design method using type. Also it takes two kinds of 8 bites full adder that is described in VerilogHDL language. Then the two programs have been emulated and synthesized under the environment of the software in Quartus Ⅱ and downloaded in an actual system. Lastly, Quartus Ⅱ has simulated the highest actual frequency of system running. By comparing the two methods, the result proves: the design method adopting the pipelining design method can improve the feasibility of the working speed of the system and there are good application prospects in the high-speed system design of this method.

关 键 词：高速通信系统 VERILOGHDL语言 硬件描述语言 流水线 设计方法 

分 类 号：TN914[电子电信—通信与信息系统] TP312[电子电信—信息与通信工程]