两相时钟方案  

Two-phase clocking

作　　者：郑兆青[1] 敖育红[2] 陈朝阳[1] 沈绪榜[1] 

机构地区：[1]华中科技大学图像识别与人工智能研究所 [2]激光技术国家重点实验室,湖北武汉430074

出　　处：《半导体技术》2003年第9期65-68,共4页Semiconductor Technology

摘　　要：选择时钟方案是同步时序集成电路设计的前提。本文阐述了两相时钟方案的规则,通过比较一相时钟与两相时钟方案,给出了两相时钟方案用于同步时序电路设计的优点。最后结合例子简要介绍了该方案在VERILOG HDL中的应用及其注意事项。Selecting one clock scheme is the basis of designing synchronous systems . Two-phase clocking disciplines was given . Two-phase clocking was compared with one-phase clockingand its merits were given. Finally, how to use VERILOG HDL to describe two-phase clocking andsome caveat combined with example are introduced.

关 键 词：两相时钟 同步时序集成电路设计 锁存器 触发器 VERILOG-HDL 

分 类 号：TN402[电子电信—微电子学与固体电子学]