高级综合中VHDL描述向Petri网转换方法的研究  

Translation of VHDL Description to Petri Net in High Level Synthesis

作　　者：刁岚松[1] 孟晗[1] 刘明业[1] 杨凯[1] 

机构地区：[1]北京理工大学ASIC研究所,北京100081

出　　处：《计算机辅助设计与图形学学报》2003年第9期1105-1111,共7页Journal of Computer-Aided Design & Computer Graphics

基　　金：国防"十五"微电子预研项目 ( 0 2 413 0 80 10 40 8)资助

摘　　要：提出一种基于执行路径的Petri网生成算法 ,该算法提取VHDL源描述中的功能和时序信息 ,生成与源描述完全等价的Petri网结构 算法采用条件树结构保存条件 ,语句执行条件和Petri网迁移条件都依据条件树生成 生成的Petri网能够准确地保存源描述中的I/O时序信息 ,形成调度过程中I/O操作处理的基础 从该结构出发 。This paper puts forward a Petri net generation algorithm based on execution paths. The algorithm extracts all functions and timing information from the VHDL description and generates Petri net as an intermediate representation identical to the VHDL description. A condition tree is used to store various conditions in a structured way. The executing conditions of all statements and transition conditions in Petri net are generated directly from the condition tree. The generated Petri net stores precisely the I/O timing information in VHDL description to guide the scheduling of I/O operation process. Based on Petri net, various I/O scheduling modes can be readily implemented.

关 键 词：专用集成电路 高级综合 VHDL PETRI网 I/O模式 

分 类 号：TN492[电子电信—微电子学与固体电子学]