CMOS结构中的闩锁效应  

Latch-up in CMOS Circuits

作　　者：陈欣 陈婷婷 

机构地区：[1]上海智芯科技有限公司,上海200233 [2]无锡华晶上华半导体有限公司,无锡214061

出　　处：《微电子技术》2003年第6期19-21,共3页Microelectronic Technology

摘　　要：本文较为详细地阐述了体硅CMOS结构中的闩锁效应 ,分析了CMOS结构中的闩锁效应的起因 ,提取了用于分析闩锁效应的集总组件模型 ,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明 ,只要让CMOS电路工作在安全区 ,闩锁效应是可以避免的 ,这可以通过版图设计规则和工艺技术 ,或者两者相结合的各种措施来实现。This paper reports that the latch-up occurred in CMOS circuit structure, which is made on silicon substrate. The reasons are analyzed; the lumped component model, which is used for analyzing the latch-up, is extracted, and the necessary conditions and the trigger mode of the latch-up are given. It is also indicated, based on analysis, that the latch-up may be avoided if CMOS circuits work in safe section, and it can be realized by taking all kinds of measures, such as adjusting the layout design rules, or the process, or adjusting the both. Finally, the key design technologies of how to prevent the latch-up are given as well.

关 键 词：CMOS集成电路 结构 闩锁效应 寄生双极型晶体管 集总组件模型 版图设计 

分 类 号：TN402[电子电信—微电子学与固体电子学]