监视跟踪定时器电路的CPLD实现  

Design of Watch-Dog Timer Circuit with CPLD

作　　者：王叶辉[1] 林贻侠[1] 严伟[1] 

机构地区：[1]上海大学微电子研究中心,上海200072

出　　处：《电子工程师》2003年第12期36-38,共3页Electronic Engineer

摘　　要：根据监视跟踪定时器的工作原理,介绍了一种实用看门狗电路的VerilogHDL设计及CPLD实现方法,结构简单、功能完善,可与任何综合库、工艺库以及FPGA/CPLD芯片结合开发出用户需要的门级网表和芯片版图,易于移植。文中还介绍了针对复杂数字系统的FPGA/CPLD开发设计的流程。The principle of supervising and monitoring operation of computer controlling system is discussed in detail in this paper. A practical Watch-Dog Timer circuit is designed in VerilogHDL, which is implemented in FPGA/CPLD. A procedure for FPGA/CPLD design is also introduced which is useful for large-scale digital system especially.

关 键 词：CPLD 硬件描述语言 监视跟踪定时器 看门狗电路 FPGA 

分 类 号：TH714.8[机械工程—测试计量技术及仪器] TP368.1[机械工程—仪器科学与技术]